Wednesday, January 7, 2009

Timing diagrams & Introduction to instruction set

TIMING DIAGRAMS
Locate the figure in the Intel documentation labeled 8085A Basic System Timing. This diagram illustrates the events in an instruction of three machine cycles. The M1 cycle is four states long, and the events at each state are shown. Notice particularly the operation of the AD0-AD7 lines, which provide the lower address byte during T1, followed by data during the later part of T2 and all of T3. Observe that the ALE line corresponds to the presentation of this low address byte. Note also that in a machine cycle in which data is going to be read, the AD lines actually capture the incoming byte during the middle of T3, and may drift around in the later part of T2. Compare this to the case of a write, in which the ‘85 presents the data byte to be written early in T2, and holds it constant until the end of T3.
Several other timing diagrams are included in the documentation which illustrate the details of each different cycle that the ‘85 can perform. These all conform nicely to the Basic System Timing diagram, with the addition of wait states, and of specific lines to perform specific functions. The Instructor will discuss these with you.
HOLD AND HALT STATES
The 8085 has provisions for the execution of a Halt instruction, which causes the system to go into T-halt states. During this time, the ‘85 is simply waiting for something to occur. There are three ways out of a Halt: A Reset, a Hold Request, and an enabled interrupt. If a Hold Request occurs during a Halt, the ‘85 will honor it by going into T-hold cycles as long as the Hold line remains asserted; it will return to the halt condition when Hold negates. If an interrupt occurs during a halt, the MP will go into an interrupt cycle if the interrupt was enabled; it will be ignored if it was not enabled. An enabled interrupt during a hold state will have to wait until the hold clears before being given control of the system. Two diagrams are included in the documentation to indicate the various combinations of hold, halt, and interrupts.
INSTRUCTION SET
The instruction set of the 8085 is identical to that of the 8080, with the exception of the addition of two instructions, RIM and SIM. The definitions of the OP codes, how they work, the operation of the condition flags, addressing modes, and the use of the H and L register pair for indirect addressing are all identical between the two processors.
The Intel documentation shows many symbols used to describe the functions and relations of parts of instructions. These include the use of lower case letters, especially the "r", to indicate a register, "rp" to indicate a register pair, "addr" to indicate an address, "data" to indicate an 8-bit data byte, "data 16" to indicate a 16-bit data word, "rh" and "rl" to indicate the high-order register and the low-order register of a register pair, respectively, and the use of some upper case, such as "PC" for program counter and "SP" for stack pointer. Many graphics symbols are used, and the instructor will now discuss them with you at length, using the documentation as reference. Be sure you understand them before proceeding.

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