Wednesday, January 7, 2009

Data Transfer Instructions Group

DATA TRANSFER GROUP
This group of instructions provides the 8085 with the ability to move data around inside the RAM, between the RAM and the registers of the MP, and between registers within the MP. They are important because a good deal of moving must be done to offset the fact that in an 8-bit byte, there is insufficient room to define the operands as specifically as is done, for example, in the PDP11. These instructions do not affect the condition codes. A few comments on the OP code groups follow:
MOV GROUP: These three instructions (MOV r1,r2, MOV r,M, and MOV M,r) are the general means of moving data between memory and registers. They move one byte with each execution. The second and third examples illustrate the use of the Register Indirect mode of addressing, in which the H&L registers of the MP contain an address, and the data is moved to or from that address. This saves space, in that the instruction is only one byte long. It requires, however, that the H&L registers be previously set up with the address required. The letter "M", when appearing as an operand in this description, specifies Register Indirect mode with H&L as the register to contain the address. No other register pair is used as such.
MVI GROUP: These two instructions (MVI r,data, and MVI M,data) provide a means of loading a byte immediately into a register or a memory address. Note that the Register Indirect mode again is evident. The immediate data is stored as a byte directly below the instruction byte.
LXI INSTRUCTION: This single instruction (LXI rp,data 16) provides a means of loading any register pair with a two-byte value. The second byte l of the instruction is loaded into the leftmost, or low-order, register of the pair, while the third byte is loaded into the rightmost, or high order, register of the pair.
LDA & STA: The Load Accumulator Direct (LDA) and the Store Accumulator Direct (STA) instructions provide a means of moving a byte between the accumulator and a RAM address. This may also be done with the MOV OP code, but only indirectly, that is, with the help of the H&L registers. The address of the byte to be loaded or stored follows the instruction, again with the inverse addressing.
LHLD & SHLD: The Load H&L Direct (LHLD) and Store H&L Direct (SHLD) instructions provide a means of moving two bytes between the HL register pair and a RAM address. Since the H&L register pair is heavily used in the Register Indirect mode, these instructions provide a quick means of loading the two bytes of an address into the pair in only one instruction. The two bytes following the instruction contain an address in RAM, again low-order in byte 2, and high-order in byte 3. For the LHLD, this address points to a single byte, which is obtained and loaded into the L register. The second byte from RAM is obtained from the address one higher than the RAM byte, and loaded into the H register. The SHLD simply stores as above, instead of loads.
LDAX & STAX: The Load Accumulator Indirect (LDAX) and Store Accumulator Indirect (STAX) instructions provide a means of moving data between the U accumulator and a memory location indirectly, with the RAM address contained in either the BC or DE register pair. This is not the same as the MOV, which uses only the HL register pair. This instruction permits the accumulator to access groups of data bytes, as may be necessary with long precision arithmetic. Obviously, the BC or DE pair must be previously loaded with the address desired.
XCHG INSTRUCTION: The Exchange (XCHG) instruction permits the HL register pair’s contents to be exchanged with the DE register pair’s contents. This allows an address to be built in the DE pair, then, when ready, to be transferred at once to the HL pair. This would be advantageous in complex data handling.

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