Wednesday, January 7, 2009

The Processor Cycle of 8085


The time required by the 8085 to fetch and execute one machine language instruction is defined as an Instruction Cycle. As in the 8080, the instructions may be of different complexities, with the result that the more complicated instructions take longer to execute. The 8085’s method of instruction execution inside the MP is more organized, however, and so the time required to execute any instruction is more predictable and more regular.
Each instruction is divided into one to five Machine Cycles. Each machine cycle is essentially the result of the need, by the instruction being executed, to access the RAM. The shortest instruction would require just one machine cycle, in which the instruction itself is obtained from RAM. The longest, of five machine cycles, would consist of five RAM accesses, the first to obtain the instruction byte itself, and the remaining four to be divided into fetching and saving other bytes. For example, cycles numbers 2 & 3 may be needed to fetch two more bytes of an address, while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM.
The type of machine cycle being executed is specified by the status lines I-O/M, S0, and S1, and the control lines /RD, /WR, and /INTA. These six lines can define seven different machine cycle types as follows. Refer to the chart in the manual which defines the bit patterns of each.
OP CODE FETCH: This is the first machine cycle of any instruction. It is defined with S0 and S1 asserted high, and I-O/M and /RD low. It is a read cycle from RAM to obtain an instruction byte.
MEMORY READ: This is a normal read cycle of any byte except the OP code. It is defined with S0 and S1 set to 0, 1 respectively, and I-O/M and /RD low. It is a read cycle from RAM to obtain a data or address byte.
MEMORY WRITE: This is a normal write cycle to memory. It is defined with S0 and S1 set to 1, 0 respectively, and I-O/M and /WR low. It is a write cycle to RAM to store one byte in the specified address.
I/O READ: This is a normal read cycle from an I/O device. It is defined with S0 and S1 set to 0, 1 respectively, and with I-O/M high and /RD low. It is a read cycle which will bring one byte into the MP from the input device specified.
I/O WRITE: This is a normal write cycle to an I/O device. It is defined with S0 and S1 set to 1, 0 respectively, and with I-O/M high and /WR low. It is a write cycle which will send one byte outbound from the MP to the specified output device.
INTERRUPT ACKNOWLEDGE: This is a response to an interrupt request applied to the MP via the INTR line. It is defined with S0 and S1 set to 1, 1 respectively, I-O/M set high, and both /RD and /WR also high. The Interrupt Acknowledge pin is also held to a low asserted level. l It is neither a read nor write cycle, although the interrupting device will jam an interrupt vector onto the D0-D7 lines on the next machine cycle.
BUS IDLE: This is an idle cycle in which no specific bus activity is defined. It occurs under three differently defined conditions:
Double Add Instruction (DAD): This instruction requires enough execution time to merit its own Idle cycle. It is defined with S0 and S1 set to 0, 1 respectively, I-O/M set low, and neither /RD nor /WR asserted (both high). Since neither a read nor a write are specified, no bus action takes place.
Acknowledge of Restart or Trap: This idle cycle allows time for the ‘85 to cope with a RST or Trap interrupt request. All bits are held high.
Halt: This idle cycle indicates that the MP has executed a Halt instruction. The I-O/M, /RD, and /WR lines are all tristated, which would allow them to be controlled by other devices. INTA is held inactive, but not tristated. The Hold line is really the proper one to use for DMA or multiple processors.
Each of the machine cycles defined above, during which an access of a RAM address or an I/O device is made (except the idle cycles), is further divided into T-states. Each T-state, for an ‘85 with a 3 MHz clock, will be about 333 nanoseconds in length. The first machine cycle, during which the OP code is being fetched, will be either 4 or 6 T-states in length. Whether 4 or 6 T-states are used depends upon whether the instruction needs further information from RAM, or whether it can be executed to completion straight away If multiple accesses are needed, the cycle will be 4 states long; if the execution can run to completion, 6 states are required. (Remember that the ‘85 is running with a faster clock, so that less time per T-state is available.)
The number of T-states for the second and succeeding machine cycles will always be 3 for normal instructions. There are two exceptions to this general rule. The first exception is in response to the request for wait states from an external device which has pulled the Ready line low. This will cause the ‘85 to insert one or more Tw states between T2 and T3, as in the 8080. The second exception is when the ‘85 is placed into the Hold condition in response to a signal from an outside device applied to the Hold line. This will be an indeterminate amount of time during which the external device will be performing a DMA function.
The documentation includes a small chart which specifies the actions of the major signals of the ‘85 during each of the 10 possible types of T-states. It may be summarized as follows:
T1 STATE: This state is the first of any machine cycle. The chart shows that S0-S1 lines, I-O/M, A8-A15, and AD0-AD7 contains whatever would be appropriate for the type of instruction being executed. (The "X" in the chart is defined as "unspecified", which translates to "whatever is normal".) The S0-S1 and I-O/M lines will define, at this early point in the machine cycle, whether the MP is attempting to address a RAM location or an I/O device. The address lines will identify the location or I/O device to be dealt with. The Address Latch Enable (ALE) line will allow some sort of external circuitry to catch and hold the contents of the AD0-AD7 lines to be used as the low byte of the address.Note that while the S0 and S1 lines may safely be ignored for general purposes, they are provided to allow the engineer to obtain an advanced warning of the type of function that will be specified during T2, i.e., a read or a write. An engineer can monitor this lines with circuitry of his own to generate his own "Early Read" or "Early Write" if he needs it for slow peripheral devices or devices. The /RD, /WR, and /INTA lines are all negated at this time. Since the AD0-AD7 lines are being used to present an address byte, it would be inappropriate to move data on the data bus; besides, it’s too early to do so. It’s also too early for /INTA. ALE, however, is asserted, since this is the time that the AD0-AD7 contents will contain the lower address byte, which must be caught and held outside the ‘85 for use by the following T-states.
T2 STATE: The chart indicates that all lines except ALE (which will be inactive for the rest of the machine cycle) will assume the proper level for the type of instruction in progress. The address lines retain the bit pattern selecting one byte from RAM or an I/O device; the AD0-AD7 lines will now prepare to either accept or present a data byte (they are in a state of transition during T2); I-O/M and the S0, S1 lines are still displaying the original settings of T1. Either /RD or /WR will assert during T2, to indicate the nature of the data transaction. /INTA will assert at T2 if an interrupt cycle has started.
WAIT STATE: If the Ready line was negated during T2, a Tw is inserted to allow the external circuitry more time to prepare for data transmission. A specific point in T2 is defined, after which a late negation of Ready will not cause the Tw to be inserted. This corresponds to the same actions in the 8080 device. All signals set up during T2 will remain constant during Tw.
T3 STATE: All lines set up during T2 will remain the same in T3, except the AD0-AD7 lines, which will be conducting data either into or out of the 8085. At the end of T3, the /RD or /WR line will negate to indicate the end of the active function. This will cause the data byte standing on AD0-AD7 to disappear.
T4 - T6 STATES: These states are required for time to permit the 8085 to continue processing internally. No bus actions are required. The S0 & S1 lines are both asserted, while I-O/M is negated, which specifies that the ‘85 is involved in an 0P code fetch. Since T4 through T6 will exist only on the first machine cycle of an instruction, this corresponds correctly with the Machine Cycle chart. The AD0-AD7 lines are tristated; the A8-A15 retain their original setting; the /RD, /WR, and INTA lines are all negated.
In addition to the T-states described above, the chart also indicates the conditions during states involved in Resets, Halts, and Holds. It must be kept in mind that during any of these, the MP clocks are still running, and the ‘85 is alive inside; it has simply shut itself off the buses to allow external events to occur. These states tristate the address, AD, I-O/M, /RD, and /WR lines to allow external devices to control them. The other lines are held at inactive levels except the S0 & S1 lines, which do indicate what type of machine cycle the system is in, i.e., whether it is a Reset, Hold, or Halt.

1 comment:

  1. very clear & simple description,really helped a lot....thnx