Wednesday, January 7, 2009

Branch Group of Instructions

BRANCH GROUP
This group of instructions permits the programmer to alter the flow of program execution from a normal straight line. There are two major types of these instructions in the 8085. The first type is the Jump, in which the flow is altered with no intention of returning to the place where the Jump occurred. The second type is the Call, which provides linking, via the system stack, to save the address of the next instruction following the Call, proceed to a subordinate routine, and return to the saved address when that routine is completed.
Further, both Jumps and Calls may be conditional or unconditional. An unconditional Jump or Call causes the function to be executed absolutely. The conditional Jump or Call causes the function to be executed if the conditions specified are met. In the first byte of these instructions, three bits labeled CCC will contain a code which specifies the conditions to be tested. These may be specified by the programmer in assembly language by putting together a mnemonic composed of a J, for Jump, or a C, J for Call, followed by one or two more characters which specify the conditions to be tested. The breakdown follows:
Mnemonic
Condition
CCC Bits
NZ
Not Zero (Z=0)
000
Z
Zero (Z=1)
001
NC
Not Carry (C=0)
010
C
Carry (C=1)
011
PO
Parity Odd (P=0)
100
PE
Parity Even (P=1)
101
P
Plus (S=0)
110
M
Minus (S=1)
111
JUMP INSTRUCTIONS: The Jump (JMP addr) and Jump Conditional (Jxx addr) instructions allow program flow to be altered by loading the contents of the two bytes following the instruction to be loaded into the Program Counter. The next instruction to be fetched, therefore, will the first of the new routine. The JMP instruction is unconditional; the Jump occurs absolutely. The Jxx instruction will alter program flow if the conditions specified by the "xx" bits are true; otherwise, program flow remains in a straight line. No condition codes are affected.
CALL INSTRUCTIONS: The Call (CALL addr) and Call Conditional (Cxx addr) instructions allow linkage to permit a subroutine to be invoked, with the address of the next sequential instruction saved for later reference. The Call will move the high byte of the PC into the address pointed to by the Stack Pointer minus 1, and the low byte of the PC into the address below that. The SP is then decremented by two, to update it to the new stack position. The two bytes following the Call instruction will then be moved to the PC, with the second byte of the instruction containing the low order byte of the address, and the third byte of the instruction containing the high order byte of the address. Thus, the address of the instruction following the Call is saved on the system stack, and the address of the first instruction of the subroutine is fetched next. The Call Conditional executes exactly the same way, providing that the conditions specified by the CCC bits are true. None of the flags are affected.
RETURN INSTRUCTIONS: The Return (RET) and Return Conditional (Rxx) instructions provide a means, at the end of a subroutine, of resuming program execution at the instruction following the Call instruction which invoked the subroutine. These instructions are placed at the end of the subroutine, not in the body of the main program. When encountered, the Return will move the byte pointed to by the Stack Pointer into the lower byte of the PC, the next byte higher in RAM to the higher byte of PC, and add 2 to the contents of SP. Thus, the address of the instruction following the Call, previously saved on the stack, is now in PC, and will be fetched next. Also, the stack pointer is updated accordingly. The Return Conditional executes exactly the same way, providing that the conditions specified by the CCC bits are true. None of the flags are affected.
RESTART: The Restart (RST n) instruction provides part of the vectored interrupt system by which any one of eight different levels of interrupt may stop the execution of the program currently in progress, save the address of the next instruction onto the stack, and then jump to any one of eight different locations in low core, depending upon the contents of the bits marked NNN in the instruction. Thus, as many as eight different external events, i.e. I/O devices, etc., may ask for service; the place where the program left off is saved; and one of eight different interrupt handling routines may be entered, which correspond to the level of the interrupt. This will be fully explained in the section on interrupts.
JUMP INDIRECT: The Jump H&L Indirect (PCHL) instruction moves the contents of the H&L registers, assumed to be a valid address, into the Program Counter. The contents of H&L must be previously built, and may be assembled by other parts of the program to the advantage of the writer. The original contents of the PC are destroyed, so this is a one-way jump.
MACHINE CONTROL GROUP
This group is a collection of miscellaneous instructions which control bodily functions of the MP, or provide utilities. Explanations follow:
PUSH AND POP: The Push Register Pair (PUSH rp) and Pop Register Pair (POP rp) instructions allow programmers to manipulate the system stack. The Push will place the contents of the BC, DE, or HL register pairs onto the stack, and update the SP accordingly. The Pop instruction will return the last two items on the stack to the specified register pair, and update the SP. The condition flags are not affected; the SP register pair may not be specified, for obvious reasons.
PSW INSTRUCTIONS: The Push Processor Status Word (PUSH PSW) and the Pop Processor Status Word (POP PSW) instructions will allow the programmer to save the contents of the A register and of the condition flags on the stack, or to retrieve them from the stack. The Processor Status Word (PSW) of the 8085 is defined as a "Flag Byte" which contains the condition flag bits in a specific sequence:
S
Z
0
AC
0
P
1
C
In addition, the contents of the A register is also saved as part of the PSW. When the PUSH PSW is encountered, the contents of the A register is pushed onto the stack first, followed by the Flag byte. The SP is then updated. When the POP is executed, the Flag byte is retrieved first, and the bits are loaded into their proper flip-flops. The A register is then loaded with the next byte retrieved. This allows programmers to save conditions at the beginning of subroutines so that the execution of the instructions within the routines will not alter the conditions under which the original program was operating.
EXCHANGE STACK TOP: The Exchange Stack Top with H&L (XTHL) instruction causes the contents of the H&L registers to be exchanged with the two bytes which are currently on the top of the system stack. These will be the last two bytes pushed. It is a two-way instruction; the stack receives the original contents of H&L, while H&L receives the two bytes from the stack. The contents of SP remain unchanged. No flags are affected.
MOVE H&L TO SP: The Move H&L Register to Stack Pointer (SPHL) instruction will directly move the contents of the H&L registers into the Stack Pointer; the original contents of SP are destroyed. This may be used to permit multiple stacks to exist at one time in the system. No flags are affected.
I/O INSTRUCTIONS
The Input (IN port) and Output (OUT port) instructions allow the MP to communicate with the outside world. In both cases, the address byte of the device to be used is contained in the byte following the instruction. This byte is presented at once to both the upper and lower bytes of the A0-A15 address lines. In the case of IN, the byte accepted on the D0-D7 data lines by the MP is placed in the A register. For the OUT, the byte to be sent on the data lines is placed in the A register prior to execution of the instruction. No flags are affected.

3 comments:

  1. thanks for this it's very much useful

    ReplyDelete
  2. Proved very useful in my projects.Thanks to the author for posting it.

    ReplyDelete
  3. Proved very useful in my projects.Thanks to the author for posting it.

    ReplyDelete