Wednesday, January 7, 2009

Data Flow in 8085

DATA FLOW

Locate the dataflow diagram in your reference manual. The dataflow of the 8085 is made up of the following units:
A General Purpose Register Array, most of which is accessible by the programmer, and which forms the essential data manipulation ability of the system;
An address generation system consisting of the Program Counter, Stack Pointer, address latches, and incrementer/decrementer. Two additional 8-bit latches are provided. The first, labeled Address Buffer, provides the upper byte of an address to the system address bus in a straight-through manner. The second, labeled Data/Address Buffer, provides the lower byte of the address early in a machine cycle; it is used later in the cycle to provide or accept an 8-bit data byte from the internal data bus of the MP to the system data bus, or from the system data bus to the MP’s data bus. This buffer therefore provides the AD0 - AD7 multiplexed address/data function mentioned above.
A mathematical and logical subsystem composed of the Arithmetic Logic Unit (ALU) and asS0ciated registers, which handle the math and logic functions of the machine;
An Instruction Register and decoder system which interpret the programmer’s instructions and implement them via nanocode;
A timing and control package which provides the bodily functions of power and clock circuits, and handles the wait, interrupt, and hold functions of the system;
An 8-bit internal data bus, which provides the data path between functional elements, and to the outside world via the Address/Data Buffer;
Interrupt control interfacing which provides both the standard 8080 interrupt structure, and 4 new interrupts which are maskable under special program controls, these last via the internal data bus;
Two serial data lines, Serial Input Data and Serial Output Data, which feed the internal data bus directly, and are serviced as part of the interrupt control structure mentioned above.
The General Purpose Register Array contains the B, C, D, E, H, and L registers, each 8 bits wide. The B and C, D and E, and H and L registers may be grouped into 16-bit register pairs. The H&L register pair may be used to store indirect addresses.
The array also contains the Program Counter (PC) and Stack Pointer (SP). These 16-bit registers contain the address of the next instruction part to be fetched, and the address of the top of the stack, respectively.
The GPR array also includes an Address Latch/Incrementer-Decrementer circuit, to make the address next required on the system address bus available to it, and to increment or decrement addresses or register contents as required.
The mathematical and logical function of the system are provided by an 8-bit Arithmetic-Logic Unit (ALU), which accepts two 8-bit arguments and generates an 8-bit result. It is fed by an Accumulator register and a Temporary register, both 8 bits wide; the result returns to the internal data bus for distribution. The ALU also has a Condition Flags register, for the storage of the conditions under which an operation ended, which may be used by following instructions. In all cases, the ALU, Accumulator, and Condition Flags function exactly as in the 8080.
The Instruction Register and Instruction Decoder accept the incoming byte from the data bus during the first machine cycle of an instruction, and interpret it by controlling the internal reS0urces of the MP as S0urces and destinations for bits and bytes. The 8085 is nanoprogram-controlled.
Acting under the direction of the instructions, the Timing and Control section of the 8085 generates the necessary timing pulses to synchronize their execution. The 8085 has its own internal oscillator, which requires only an external crystal to generate the clocks. The internal workings of the ‘85 require only a single phase clock, with a 50% duty cycle, which minimizes system timing requirements. This clock is made available to the outside world to allow external functions to be synchronized to the MP’s cycles.
Ready - Wait functions are provided in the ‘85. If a memory circuit’s response time is such that the MP will expect data before the RAM is ready to respond, the memory subsystem may request a Wait State (Tw) by pulling the Ready line low. This must be done prior to a certain point in the machine cycle. This function is important because the ‘85 is designed to work at 3 MHz, decreasing the time within which the RAM may respond.
The Timing and Control section of the ‘85 also provides several native signals, both inbound and outbound, which interface with the external world, and provide control signals and timing to the three-bus architecture. This makes way, then, for the multiplexing of the address and data on the AD0-AD7 lines. These lines include /Read, /Write, and I-O/M, which indicate whether the function to be performed is a input or an output, and whether it is addressed to memory or an I/O device; Address Latch Enable and two status lines so and S1, which advise the external world of the status of each machine cycle of the 8085; Hold and Hold Acknowledge, which allow the external I/O to ask for and receive a DMA cycle; and Reset In and Out, which provide the reset.
The 8085 also supports the interrupt structure of the 8080, with the Interrupt and Interrupt Acknowledge lines. In the ‘85, however, these lines are made available to the internal data bus of the MP instead of being connected directly to the Timing and Control logic. The external circuits see the operation of them as the same, however. In addition, four more interrupts are available, also connected to the data bus inside the MP, but these are under special software control with two OP codes. The reason for the placement of the interrupts onto the data bus will be shown later.
Two I/O lines are provided on the ‘85 which allow a single bit to be tested or presented directly by the MP. The Serial Data In (SID) and Serial Data Out (SOD) lines may be sensed or driven under program control via the same two instructions included for the new interrupt scheme. They allow the MP to treat them as either true serial data I/O, if programmed timing loops are included, or as simple single bit test or control ports for the sensing or control of external events.

No comments:

Post a Comment