Wednesday, January 7, 2009

Adressing Modes & Branch Instruction Types

ADDRESSING MODES
The 8085 provides four different modes for addressing data, either in its registers or in memory. These are described below:
DIRECT MODE - This mode creates instructions three bytes long. The first byte contains the operation to be performed. The second and third bytes contain the address in memory where the data byte may be found. Thus, the instruction directly specifies the absolute location of the data. Note that the second byte of the instruction contains the low order byte of the address, while the third byte contains the high order byte of the address. This illustrates the inverse addressing of the device.
REGISTER MODE - This mode results in single-byte instructions. The byte contains bits which specify a register or register pair in which the data is located.
REGISTER INDIRECT MODE - This mode results in single-byte instructions. The byte contains bits which specify a register pair, which in turn contains the address of the data in memory. Thus, the instruction indirectly specifies the address of the data by referring to a register pair for the absolute address. Note that the high order byte of the address is stored in the leftmost register of the pair, while the low order byte of the address is stored in the rightmost register of the pair. The address 3000H, therefore, would be stored in the HL register pair as 30 in H, and 00 in L.
IMMEDIATE MODE - This mode results in a two or three byte instruction. The first byte contains the instruction itself. The second and third bytes contain the immediate data, either as a single 8-bit value, or as a 16-bit value. If the 16-bit value is used, the bytes are reversed as discussed previously, with the second byte containing the low order byte, and the third byte containing the high order byte.

BRANCH INSTRUCTION TYPES
Normal execution of instructions is in a straight line. Branch instructions are available to alter the course of execution flow. These instructions can specify the address of the next instruction to be executed, if it is not the one immediately following the branch, in two ways:
DIRECT BRANCH - In this mode, the branch contains the address to be used, if the branch occurs, as two bytes following the instruction byte. The second byte contains the low order byte, while the third byte contains the high order byte.
REGISTER INDIRECT BRANCH - In this mode, the branch specifies a register pair which will contain the address for the branch. This address must obviously be set up prior to the branch occurring. The register pair contains the high order byte of the address in the first, or right-most register of the pair, and the low order byte of the address in the second, or left-most register of the pair, in order to maintain alignment with the general addressing scheme.
The Intel documentation divides the 8085’s instruction set into five groups. These are the Data Transfer Group, Arithmetic Group, Logical Group, Branch Group, and a Machine Control-I/O Group. These will now be discussed individually, with specific instructions mentioned for illustration in these notes. The entire set will be reviewed by the instructor as this section progresses.

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