Wednesday, January 7, 2009

Interfacing The 8085

INTERFACING THE 8085

A brief description of the signals between the 8085 and the outside world follows. Refer to the reference manual for pin-outs and details.
ADDRESS LINES A8 - A15: These tristate lines are outbound only. They provide the upper 8 bits of the 16-bit-wide address which identifies one unique 8-bit byte within the MP’s address space, or the 8-bit address of an I/O device. Sixteen address lines provide an address space of 65,536 locations.
ADDRESS-DATA LINES AD0 - AD7: These tristate lines may by either inbound or outbound. They provide a multiplexing between the lower 8 bits of the 16-bit-wide address early in a machine cycle and 8 data bits later in the cycle. When containing addresses, these lines are outbound only; when containing data, they may be either inbound or outbound, depending upon the nature of the machine cycle. They also will contain the 8 bits of an I/O device address during an I/O operation.
ADDRESS LATCH ENABLE (ALE): This signal appears outbound early in a machine cycle to advise the external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a memory address. It should be used to clock a catch-and-hold circuit such as a 74LS245 or 74LS373, so that the full address will be available to the system for the rest of the machine cycle. The documentation states that the falling edge of ALE is the point at which the signals on the AD lines, as well as the so, S1, and I-O/M lines (below) will be stable and may be taken by the external circuitry.
STATUS LINES so, S1, & I-O/M: These three status lines serve to indicate the general status of the processor with respect to what function the MP will perform during the machine cycle. The so and S1 lines are made available for circuits which need advanced warning of the ensuing operation, such as very slow RAM or other specialized devices. The system may not normally need to monitor these lines. The I-O/M line approximates in one line what the so and S1 lines do in two. It indicates whether the operation will be directed toward memory (line is low), or toward I/O (line is high). Refer to the manual for a full explanation.
READ & WRITE (/RD & /WR): These lines indicate which direction the MP expects to pass data between itself and the external data bus. Read indicates that the MP is expecting data to be fed to it; Write indicates that the MP is going to send data away from itself. These lines also serve to time the event, as well as identify its direction.
READY: This is an input line which may be used as a signal from external RAM that a wait state is needed, since the RAM is not able to provide the data or accept it in the time allowed by the MP. The negation of Ready, by being pulled low, will cause the 8085 to enter wait states. See the timing diagrams for critical timing.
HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA): These lines provide the 8085 with a DMA capability by allowing another processor on the same system buses to request control of the buses. Upon receipt of HOLD, the ‘ 85 will tristate its address, data, and certain control lines, then generate HLDA. This signals the other processor that it may proceed. The ‘85 will remain off the buses until HOLD is negated.
INTERRUPT & INTERRUPT ACKNOWLEDGE (INTR & INTA): These lines provide a vectored interrupt capability to the 8085. Upon receipt of INTR, the ‘85 will complete the instruction in process, then generate INTA as it enters the next machine cycle. The interrupting device will jam a Restart (RST) instruction onto the data bus, which the ‘85 uses to locate an interrupt vector in low RAM.
RST 5.5, 6.5, 7.5: These three lines are additional interrupt lines which generate an automatic Restart, without jamming, to vectors in low RAM which are between those used by the normal INTR instruction. The 5.5 line, for example, will cause an automatic restart to a 4-byte vector located between 5 and 6 of the normal vectors used by INTR. These lines have priority over the INTR line, and each other. They also have certain electrical characteristics for assertion, and may be masked off or on by software. More on the 8085’s interrupts later.
TRAP: This is an unmaskable interrupt with a fixed vector in low RAM. See the interrupt discussion later in the notes.
RESET IN & RESET OUT: These lines provide for both MP and system reset. The reset circuitry in the 8224, used with the 8080, has been brought inside the MP. The RESET IN line is generated asynchronously by some sort of external circuit, such as an RC network or Reset switch. Upon receipt of this signal, the ‘85 will internally synchronize the Reset with the clock of the processor, then generate RESET OUT for other devices in the system. See the reference manual for details.
X1 & X2: These two pins provide connection for an external frequency determining circuit to feed the 8085’s clock. This is normally a crystal, although other resonant circuits may be used. X1 alone may be used as a single input from an external oscillator. The internal oscillator of the ‘85 will divide the frequency by two for the system clock.
CLOCK (CLK): This line provides a system clock signal to external circuits which need to be in synchronization with the MP.
SERIAL INPUT DATA & SERIAL OUTPUT DATA (SID & SOD): These two lines provide for a single serial input or output line to/from the 8085. These lines are brought into the device as D7, and may be tested or set by the Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions. These two instructions also have control over the mask which controls the RST 5.5, 6.5, and 7.5, and TRAP, interrupts. The SID and SOD lines are simple single bit I/O lines; any timing required to provide external communication via them must be provided by the software.
· Vcc & Vss: These are the power connections for +5 volts and ground, respectively.

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