General Description about 8085

GENERAL DESCRIPTION
The Intel 8085 microprocessor is an NMOS 8-bit device. Sixteen address bits provide access to 65,536 bytes of 8 bits each. Eight bi-directional data lines provide access to a system data bus. Control is provided by a variety of lines which support memory and I/O interfacing, and a flexible interrupt system. The 8085 provides an upward mobility in design from the 8080 by supporting all of the 8080’s instruction set and interrupt capabilities. At the same time, it provides cleaner designs by virtue of a greater on-device component density, and by requiring only a 5 volt supply. In addition, the 8085 is available in two clock speeds.
The 8085 comes in two models, the 8085A and the 8085A-2. The 8085A expects a main clock frequency of 3 MHz, while the 8085A-2 expects a main clock frequency of 5 MHz. In both cases, the clock is a single phase square wave. This single clock is generated within the 8085 itself, requiring only a crystal externally. This eliminates the need for an external clock generator device. In all other respects, the A and A-2 devices are identical.
The 8085 supports the interrupt structure of the 8080, including the RST instruction and the eight vectors. It extends these by the addition of four more interrupts, each with their own pins, three of which are maskable, and which use vector areas between the existing ones of the 8080. The 8085 is adaptable for use with the 8259 Priority Interrupt Controller, a programmable device. It is possible, upon an interrupt from this device, to jam either a RST instruction onto the data lines, or a CALL instruction to any location in RAM directly.
The 8085 has two pins dedicated to the generation or reception of serial data. While these do not constitute a complete serial I/O system, they do allow the MP to send and receive serial bits, albeit with a large software overhead. The 8085 therefore finds itself useful as a complete control device for remote control applications.
The 8085 supports the entire 8080 instruction set. In addition, two new instructions are added. These instructions permit software control over the extended interrupt capabilities of the ‘85, by making the new interrupts both maskable and interrogatable. The masks can be set, examined, etc.. The same instructions also allow investigation of the serial input line, and generation of conditions on the serial output line.
Unlike the 8080 which had discrete pins for the address and data busses, the 8085 make use of multiplexing of the lower 8 bits of the address with the data bits on the same 8 pins. This requires that the external circuitry be able to catch and hold the A0-A7 lines for later use. The upper 8 bits of the address have their own pins, however. Three primary control bus lines allow the device to identify whether the cycle in progress is for RAM or I/O, and whether it is a Read or a Write. Two status pins are provided, to allow advance knowledge of certain events in multiprocessor applications.
The internal timing of the device makes use of machine cycles in which, in almost every case, a bus cycle is involved. Each machine cycle consists of several T-states, which are defined by the clock input signal. Thus, many clock cycles are needed to effect one complete instruction. The 8085 has many new support devices to ease design work. These include the 8259 Programmable Interrupt controller, the 8202 Dynamic RAM controller, plus several new I/O devices with various amounts of RAM, ROM, parallel I/O, and timer-counters. The general approach was to make the device as compatible with the Multibus architecture as possible.