8085 Interrupt Types

8085 TYPE INTERRUPTS

The 8085 has facilities for servicing interrupts similar to the 8080. The functional items required are an Interrupt Request (INTR) pin, an Interrupt Acknowledge (INTA) pin, an Interrupt Enable (INTE) pin, eight interrupt vectors in low RAM, and the Restart instruction. These perform in the same way as the 8080 interrupt system. Here is a brief review:
1. A program is running normally in the system. The 8214 Priority Interrupt Controller or similar circuit has its compare mask set to some priority level. The Interrupt Enable bit has been set on by some previous routine, enabling interrupts.
2. A device wishes to interrupt the system. It raises its own line which connects directly to the 8214. The 8214 compares this request with the current status of the system. If the new request is higher in priority than the existing (if any), the interrupt will be allowed. If not, the interrupt will be latched for later use, but no further action is taken.
3. The Interrupts Enabled line exiting the 8085 is high, indicating that interrupts are permitted. The 8214 raises the Interrupt line, which causes the MP to finish the current instruction, and then enter an interrupt service cycle. The MP generates the Interrupts Acknowledge line at the beginning of this cycle to permit the 8214 to proceed.
4. Upon receipt of the INTA line, the 8214 along with an 8212 octal latch or similar circuit, generates a Restart instruction which it jams onto the data bus at T3 of the interrupt service cycle. The MP receives this, and removes from it the three-bit modulo-8 vector, which it then multiplies by 8 to find the vector in low RAM. This vector contains one or more instructions which can service the device causing the interrupt.
5. The execution of the Restart instruction causes the address of the next normal instruction to be executed, obtained from PC, to be placed onto the stack. The next machine cycle will be the M1 of the instruction located in the vector in low RAM. This instruction can now guide the MP to the routine to service the interrupt.
6. At the end of the interrupt service routine, a Return (RTN) instruction will cause the popping of the address off the stack which was of the next instruction to be serviced if the interrupt had not occurred.
The system now finds itself back where it came from.
There are three possible variations to the above scenario. First, unlike the 8080, the 8085 will permit the interrupt as described above as long as no other interrupts are pending which are of greater importance. These, of course, are the 5.5, 6.5, 7.5, and Trap. If any of these are pending, they will be serviced first.
Secondly, while the 8214 was the original device to service interrupts on the 8080 system, the 8085 can work with the 8259A Programmable Interrupt Controller as well. This is a more complex device, programmable as to how it handles interrupts, and stackable to two levels, providing as many as 64 levels of interrupt for the ‘85. The 8259A, moreover, generates Call instructions as well as Restarts. This means that a Call may be jammed onto the data bus during T3 of the interrupt cycle, instead of Restart. While the Restart provides a vector to eight different places in low RAM, depending upon the modulo-8 bits it contains, the Call contains a full two-byte-wide address, which can effectively vector the MP to any-place within the 64K RAM address space. This obviously provides a vastly extended ability to handle interrupts more efficiently.
The third item to be aware of is that the Interrupt Enable flip-flop of the 8080 is now observable as the IE bit #3 of the byte obtained by executing the RIM instruction. It hitherto has not been available, and its status must be remembered by the programmer. Now the bit may be checked with the RIM instruction, to aid in programming.

MASKABLE INTERRUPTS

Three maskable interrupts are provided in the 8085, each with their own pins. They are named RST 5.5, RST 6.5, and RST 7.5, respectively. To see where these names come from, study this chart:
NAME: ADDRESS:
RST 0 00H
RST 1 08H
RST 2 10H
RST 3 18H
RST 4 20H
TRAP 24H
RST 5 28H
REST 5.5 2CH
RST 6 30H
RST 6.5 34H
RST 7 38H
RST 7.5 3CH
Note in the chart that the items in light face are those with which we are already familiar. They are the normal vectors for the Restart instructions 0 through 7, as created by the 8214. They are 8 bytes apart, which is ample room for such jumps as are needled to obtain the interrupt servicing routines.
Now look at the bold face items. These items have vector areas which are between the original vectors in RAM. 12he 5.5, for instance, is half way between the RST 5 and the RST 6 vectors, hence the ".5". If all the vectors were in use, those located above address 20H would each have only four bytes in which to locate and jump to the interrupt service routine. This should be enough room, however, if used wisely. Note also that the Trap interrupt is located at the 4.5 point in the vectors.
The 5.5, 6.5, and 7.5 vectors have several items in common. First, they each have their own pin directly into the 8085. These pins will accept asynchronous interrupt requests without the need for any sort of external priority interrupt device. Secondly, these interrupts are individually maskable. This is accomplished via the Set Interrupt Mask instruction. This instruction allows bits to be set or cleared which will permit or deny an interrupt on one of these lines to force the ‘85 into an interrupt service cycle. When an input is received on one of these lines and its respective mask bit is enabled (set to 0), the processor will finish the current machine cycle, then enter a interrupt service cycle in which an automatic jam inside the MP will vector it to 2CH, 34H, or 3CH for 5.5, 6.5, or 7.5 respectively. Those locations will assumedly have been previously set to contain directions to the interrupt servicing routines.
The RST 5.5 and RST 6.5 interrupts are "level sensitive" This means that the device wishing to interrupt will apply a steady high level to the appropriate pin and hold it there until the 8085 gets around to responding. When the ‘85 recognizes the applied high level, it will permit the interrupt to be serviced in the next machine cycle. The mask bits set by the SIM instruction will directly determine what the RIM instruction sees with respect to the 5.5 and 6.5 interrupt pending bits. If the mask bits are set high (to a 1), these interrupts are masked off. This means that a following RIM will not see them as pending. If the mask bits are set to 0 (enabled), a RIM will see the true condition in bits 4 and 5 of the mask byte.
The RST 7.5 interrupt is "edge sensitive". This means that a pulse applied to this pin, requesting an interrupt, can come and go before the processor gets around to servicing it. This is possible because, unlike the 5.5 and 6.5, the 7.5 has a flip-flop just inside its pin which instantly registers the fact that an interrupt request, albeit short, was applied to the device. This flip-flop provides a bit which is read in RIM instruction as bit 6. This bit will indicate an interrupt pending if a quick pulse is applied to pin 7.5, even though bit 2 of the SIM instruction, the 7.5 mask bit, is turned on (disabled). Bit 2 of SIM byte, therefore, acts differently as a mask bit than does bits 0 and 1 for 5.5 and 6.5. Whereas bits 0 and 1 will mask off all indication of action on pins 5.5 and 6.5, bit 2 will allow the indication of a 7.5 interrupt pending, but will prevent the actual servicing of the 7.5 vector unless the mask is enabled for it. In this way, even though the mask set by the SIM prevents the MP from servicing a 7.5 interrupt, the fact that such an interrupt did occur, captured by the flip-flop, is indicated to whatever routine next executes a RIM instruction.
While the normal interrupt and 5.5 and 6.5 interrupts’ enable bits are reset when these are serviced, the 7.5 interrupt flip-flop must be turned off individually. This may be accomplished by actually responding to the interrupt, just like the other interrupts above; by having the 8085 receiving a /RESET IN, which would also reset the whole system; or by executing a SIM instruction in which bit 4 of the SIM byte is set on. This bit 4 is the "Reset RST 7.5" bit, and will reset the flip-flop if it is on when a SIM is executed.

NON-MASKABLE INTERRUPT

The Trap instruction is a non-maskable interrupt provision for the 8085. There is no mask bit related to it, and no control bits of any kind. It is used for interrupts of a catastrophic nature, such as the impending doom of a power failure. It is essentially an edge-sensitive input, since its pin connects directly inside the ‘85 to a flip-flop to capture the fact that a request was made. However, the inside circuitry around the flip-flop requires that although the flip-flop is set, the asserted level be continually applied thereafter until the processor enters the service cycle. This is shown in a diagram in the documentation. The Trap, therefore, is called both edge-sensitive and level sensitive as well. The order of priority for all of the interrupts of the 8085, from least important to most important, are the Restart 0 through Restart 7, RST 5.5, RST 6.5, RST 7.5, and finally the Trap. Remember that through the use of the 8214, the RST 0 through 7 interrupts are also prioritized, with 0 as the least important and 7 as the most important. Collectively, the 8085 has a complete set of interrupt capabilities that should serve every need.