Wednesday, January 7, 2009

Introduction to 8085 Microprocessor

Intel 8085 microprocessor is the next generation of Intel 8080 CPU family. In addition to being faster than the 8080, the 8085 had the following enhancements:

  • Intel 8085 had single 5 Volt power supply.
  • Clock oscillator and system controller were integrated on the chip.
  • The CPU included serial I/O port.
  • Two new instructions were added to 8085 instruction set.

The CPU also included a few undocumented instructions. These instructions were supposed to be a part of the CPU instruction set, but at the last moment they were left undocumented because they were not compatible with forthcoming Intel 8086.


Full list of differences between Intel 8080 and 8085 processors.


There were multiple versions of 8085 microprocessors. The original version of the 8085 microprocessor without suffix "A" was manufactured by Intel only, and was very quickly replaced with 8085A containing bug fixes. A few years after that, around 1980, Intel introduced 8085AH - HMOS version of 8085A. There was also 80C85A - CMOS version of the 8085A. It's not clear if 80C85 was ever manufactured by Intel or not, but it was produced by at least two second source manufacturers - OKI and Tundra Semiconductor. Tundra Semiconductor manufactured the fastest 8085 microprocessor running at 8 MHz.
Second source manufacturers: AMD, Mitsubishi, NEC, OKI, Siemens, Toshiba. Soviet Union also manufactured clones of Intel 8085 CPU.

ARITHMETIC

The arithmetic instructions usually include addition, subtraction, division, multiplication, incrementing, and decrementing although division & multiplication were not available in most early CPU’s. There are two flags used with arithmetic that tell the program what was the outcome of an instruction. One is the Carry (C) flag. The other is the Zero (Z) flag. The C flag will be explained in the following example of addition. The Z flag, if set, says that the result of the instruction left a value of 0 in the accumulator. We will see the Z flag used in a later lesson.
Addition
This is straightforward and is simply to add two numbers together and get the result. However there is one more thing. If, in the addition, the result was too big to fit into the accumulator, part of it might be lost. There is a safeguard against this. Take the case of 11111111b (255) and 11111111b (255). These are the largest numbers that can fit into an 8-bit register or memory location. You can add these as decimal numbers, since I gave you their values in decimal also, and you would get 510. The binary value for 510 is 111111110b (9 bits). The accumulator is only 8 bits wide, it is a byte. How do you fit a 9-bit number into 8 bits of space? The answer is, you can't, and it’s called an OVERFLOW condition. So how do we get around this dilemma? We do it with the CARRY (C) flag. If the result of the addition is greater than 8 bits, the CARRY (C) flag will hold the 9 th bit. In this case the accumulator would have in 11111110b (254) and the C flag would be a 1, or set. This 1 has the value of 256 because this is the 9th bit. We haven't covered a 9-bit number, but they come up all the time as overflows in addition. Since we are using base 2, and we found out in lesson 2 that the 8th bit (bit 7) in a byte is worth 128, then the 9th bit is worth 2 times that, or 256. Adding 254 and 256, we get 510, the answer, and we didn't loose anything, because of the C flag. Had the result of the addition not caused an overflow, the C flag would be 0, or cleared.

Subtraction

In the case of subtraction, the process is more difficult to explain, and as such, I'm not going to cover it here. It involves 1's compliment and 2's compliment representation. But I will tell you this, you can subtract two numbers and if there is an under flow, the C flag will be a 1, otherwise it will be a 0. An under flow is where you subtract a larger number from a smaller number.
Multiplication and Division
In the micro we will be using, the 8085, multiply and divide instructions are not available so we will wait till later (EL31G-Microprocessors II) to talk about them. They do, however, do just what the names suggest.
Increment & Decrement
Two other instructions are included in the arithmetic group. They are increment and decrement. These instructions are used to count events or loops in a program. Each time an increment is executed, the value is incremented by 1. A decrement, decrements the value by 1. These can be used with conditional jumps to loop a section of program, a certain number of times. We will see these used later.

LOGICAL

In micros there are other mathematical instructions called logical instructions. These are OR , AND, XOR, ROTATE, COMPLEMENT and CLEAR. These commands are usually not concerned with the value of the data they work with, but, instead, the value, or state, of each bit in the data.
OR

The OR function can be demonstrate by taking two binary numbers, 1010b and 0110b. When OR'ing two numbers, it doesn't matter at which end you start, right or left. Let's start from the left. In the first bit position there is a 1 in the first number and a 0 in the second number. This would result in a 1. The next bit has a 0 in the first number and a 1 in the second number. The result would be 1. The next bit has a 1 in the first number and a 1 in the second number. The result would be a 1. The last bit has a 0 in the first number and a 0 in the second number, resulting in a 0. So the answer would be 1110b. The rule that gives this answer says that with an OR, a 1 in either number result in a 1, or said another way, any 1 in, gives a 1 out.

AND

AND'ing uses a different rule. The rule here is a 0 in either number will result in a 0 , for each corresponding bit position. Using the same two numbers 1010b and 0110b the result would be 0010b. You can see that every bit position except the third has a zero in one or the other number. Another way of defining an AND is to say that a 1 AND a 1 results in a 1.

XOR (eXclusive OR)

XOR'ing is similar to OR'ing with one exception. An OR can also be called an inclusive OR. This means that a 1 in either number or both will result in a 1. An eXclusive OR says that if either number has a 1 in it, but not both, a 1 will result. A seemingly small difference, but crucial. Using the same two numbers, the result would be 1100b. The first two bits have a 1 in either the first or the second number but not both. The third bit has a 1 in both numbers, which results in a 0. The fourth has no 1's at all, so the result is 0. The difference may seem small, even though the OR and XOR result in different answers. The main use of an XOR is to test two numbers against each other. If they are the same, the result will be all 0's, otherwise the answer will have 1's where there are differences.

Compliment

Complimenting a number results in the opposite state of all the 1's and 0's. Take the number 1111b. Complimenting results in 0000b. This is the simplest operator of all and the easiest to understand. Its uses are varied, but necessary, as you'll see later.
Rotate
These instructions rotate bits in a byte. The rotation can be left or right, and is done one bit each instruction. An example might be where the accumulator has a 11000011b in it. If we rotate left, the result will be 10000111b. You can see that bit 7 has now been moved into bit 0 and all the other bits have move 1 bit position in, the left direction.

Clear

This instruction clears, or zero's out the accumulator. This is the same as moving a 0 into the accumulator. This also clears the C flag and sets the Z flag.

BRANCHING

There are also program flow commands. These are branches or jumps. They have several different names reflecting the way they do the jump or on what condition causes the jump, like an overflow or under flow, or the results being zero or not zero. But all stop the normal sequential execution of the program, and jump to another location, other than the next instruction in sequence.

Jump on Condition (of a Bit)

These instructions let you make a jump based on whether a certain bit is set (a 1) or cleared (a 0). This bit can be the CY (carry) flag, the Z (zero) flag, or any other bit.


Call

There is also a variation on a jump that is referred to as a CALL. A CALL does a jump, but then eventually comes back to the place where the CALL instruction was executed and continues with the next instruction after the CALL. This allows the programmer to create little sub-programs, or subroutines, that do repetitive tasks needed by the main program. This saves programming time because once the subroutine is written, it can be used by the main program whenever it needs it, a kind of way to create your own instructions.

Overview

Memory
Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.
Interrupts
The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:
One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).

CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address.

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

I/O ports
256 Input ports256 Output ports

Registers
Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
Flag is an 8-bit register containing 5 1-bit flags:
Sign - set if the most significant bit of the result is set.
Zero - set if the result is zero.
Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
Parity - set if the parity (the number of set bits in the result) is even.
Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:
8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.

Program counter is a 16-bit register.

Memory and Addressing

Memory and Addressing

There are several different types of memory in a micro. One is Program memory. This is where the program is located. Another is Data memory. This is where data, that might be used by the program, is located. The neat (or strange) thing is that they both reside in the same memory space and can be altered by the program. That’s right, a program can actually alter itself if that was necessary. Two terms are used when talking about memory. Reading (load) is getting a value from memory and Writing (store) is putting a value into memory.
There are three buses (not the kind you ride in) associated with the memory subsystem. One is the address bus, the second is the data bus, and the third is the control bus. It's important for you to know exactly how all this works, because these busses transport data and addresses everywhere. All three are connected to the memory subsystem. Its also good to know the function of each to better understand what's happening. In the 8085 CPU, the address bus is 16 bits wide. It acts to select one of the unique 216 (64K) memory locations. The control bus determines whether this will be a read or a write. In the case of an instruction fetch, the control bus is set up for a read operation. Data is read or written through the data bus, which is 8 bits wide. This is why all registers and memory are 8 bits wide, it's the width of the data bus on the 8085 CPU. A bus is just a group of connections that all share a common function. Instead of speaking of each bit or connection in the address separately, for example, all 16 are taken together and referred to simply as the address bus. The same is true for the control and data buses.
A byte is the most used number in a micro because each memory location or register is one byte wide. Memory has to be thought of as a sort of file cabinet with each location in it being a folder in the cabinet. In a file cabinet, you go through the tabs on the folders until you find the right one. To get to each memory location, a different method is used. Instead, a unique address is assigned to each location. In most micros this address is a word or 16 bits, or 4 digit hex. This allows for a maximum of 65536 (216 or 64K) unique addresses or memory locations that can be accessed. These addresses are usually referred to by a 4 digit hex number. Memory usually starts at address 0000h and could go up to FFFFh (216 or 64K or 65536 in total). To access these locations, a 16 bit address is presented to memory and the byte at that location is either read or written.
The Program Counter is what holds this address when the micro is executing instructions. The reason instructions are read sequentially, is because the program counter automatically increments after fetching the current instruction. It does this even before the current instruction is acted upon. The sequence is that the program counter's contents are placed on the memory address bus and the instruction is fetched from memory through the data bus, and immediately the program counter is incremented by 1. Then the micro looks at the instruction and starts processing it. If the instruction is not some kind of jump or call, the instruction is completed and the program counter is presented to the memory address bus again and the next instruction is fetched, the program counter is incremented and the process starts over. This is referred to, in computer jargon, as fetch, decode, and execute.
In the case of reading or writing data, the process is a little different. Data can be read from or written to memory in similar fashion to the fetch. But data does not need the decode & execute steps.

The 8085 Processor

The 8085 Microprocessor

The INTEL 8085 microprocessor. This chip was the last 8-bit general purpose CPU made by INTEL and has 40 pins.
The address bus requires 16 pins and the data bus requires 8 pins but INTEL cleverly decided to share or multiplex these two busses so the data bus share the lower (A0-A7) 8 pins of the address bus. This caused no problem since address and data are never on the bus at the same time.
Two pins are for serial communications with the 8085. Through these pins, serial data can be sent or received with another computer. This is how we will load a program into the 8085 kit used in the lab, from a PC.
Five more pins are for a different kind of input called interrupts. In our example in lesson 1 of the program where we are standing at the street corner, watching the light and the traffic, if a person walked up and tapped us on the shoulder and asked what time it is, this would be an example of an interrupt. It doesn't alter the program we are doing, it just temporarily stops us while we tell the time to the person. As soon as we tell the time, we go back to watching the lights and traffic as before. This describes the action of an interrupt.
The interrupt has a program associated with it to guide the micro through a problem. In the case of the above example, this program would be to look at our watch, read the time, and then tell it to the person. This is called an interrupt service routine (ISR). Each time an interrupt occurs, the current program is temporarily stopped and the service routine is executed and when complete, returns to the current program. We will spend a lot more time later describing interrupts and how we'll use them.
Inside the 8085 there are 10 seperate registers. They are called A, B, C, D, E, H, L, PSW, PC, and SP. All but the PSW, PC, and SP registers are used for temporary storage of whatever is needed by the program. The accumulator called A is also different from the other registers. It is used to accumulate the results of various instructions like add or sub (subtract). The Program Counter (PC) we have already mentioned while the Stack Pointer (SP) actually holds addresses and is 16 bits wide. All the others are 8 bits wide.
There are other features to be covered later, as they come up. In the next lesson we will start looking at assembly language, the method we will use to write a program.

What is assembly Language ?

What is Assembly Language?

Inside the 8085, instructions are really stored as binary numbers, not a very good way to look at them and extremely difficult to decipher. An assembler is a program that allows you to write instructions in, more or less, English form, much more easily read and understood, and then converted or assembled into hex numbers and finally into binary numbers.
The program is written with a text editor (NOTEPAD or similar), saved as an ASM file, and then assembled by the assembler (TASM or MASM or similar) program. The final result is an OBJ file you download to the 8085. Here is an example of the problem of adding 2 plus 2:
mvi A,2 ; move 2 into the A registermvi B,2 ; move 2 into the B registeradd B ;add reg. B to reg. A, store result in reg. A

The first line moves a 2 into register A. The second moves a 2 into register B. This is all the data we need for the program. The third line adds the accumulator with register B and stores the result back into the accumulator, destroying the 2 that was originally in it. The accumulator has a 4 in it now and B still has a 2 in it. In the program above all text after the ‘;’ are treated as comments, and not executed. This is a very important habit to acquire.
Assembly language follows some rules that I will describe as they come up. With most instructions, especially those involving data transfer, the instruction is first, followed by at least 1 space, then the destination followed by a comma, and then the source. The destination is where the result of the instruction will end up and the source is where the data is coming from.
Next we will read a switch, and light an LED if the switch is pressed. This happens quite often in your lab experiments. Bit 0 of Port 0 will be the switch. When the switch is closed or pressed, bit 0 will be a 1, and if the switch is open or not pressed, bit 0 will be a 0.
Bit 0 of Port l be the LED. If bit 0 is a 0 the LED is off and if bit 0 is a 1, the LED will be on. All the other bits of reg. A will be ignored and assumed to be all 0's, for the sake of discussion
start: IN 0 ; read Port 0 into reg. A
CMP 1 ; compare reg. A with the value 1
JNZ start ; jump to start if the comparison does not yield 0
OUT 1 ; send a 1 to Port 1, turning the LED on
JMP start
The first line has something new. It's called a label. In this case it is start: . A label is a way of telling the assembler that this line has a name that can be referred to later to get back to it. All labels are followed by the symbol : , which tells the assembler that this is a label. In the first line we also read the switch by reading Port and putting it into the accumulator. Reg. A is the only register that can read in/send out data via ports or perform compares. Thus, we need not write ‘A’ in the command…it’s implied!
The next line compares the value in reg. A with the value 1. If they are equal, the Zero flag is set (to 1). The next line then jumps to start: only if the Zero flag is not set ie: the value in reg. A is not 1 therefore the switch was not pressed. The program will therefore keep looping until the switch is pressed!
If the switch is pressed then the penultimate line writes the value 1 to the accumulator, therefore bit 0 = 1, and the LED comes on.
The last line jumps back to start. This completes the loop of reading the switch and writing to the LED.
This particular problem could have been solved with just a switch connected to an LED, like a light is connected to a wall switch in your house. But with a micro in the loop, much more could be done. We could have a clock that also turns on and off the LED based on time. Or we could monitor the temperature and turn the LED on and off based on what temperature it is. Or we could monitor several switches and turn the LED on and off based on a combination of switches, etc….it’s up to the imagination what can be controlled.
In the above example we assumed that the other bits of ports 0 and 1 were all zeros. But in reality, each of these bits could have a function assigned to them. Then we would need to look only at bit 0 in port 0 and bit 0 in port 1. This further complicates the problem. Also, we assume that port 0 was previously defined as an input port whereas port 1 was defined as an output port.
In assembly we can assign a name to a port and refer to it by that name, instead of port 0 or port 1. This is done with an equate directive. Directives are assembler commands that don't result in program but instead direct the assembler to some action. All directives start with a period.
.equ switch, 0 ;port 0 is now called switch
.equ LED,1 ;port 1 is now called LED
start: IN switch ; read Port 0 into reg. A
CMP 1 ; compare reg. A with the value 1
JNZ start ; jump to start if the comparison does not yield 0
OUT LED ; send a 1 to Port 1, turning the LED on
JMP start
This has the same result as the previous program. Also the equate only has to be made once at the start of the program, and thereafter the name or label is used instead of the port number. This makes things much simpler for the programmer. All equates must be defined before they are used in a program. This holds true for labels also. Another advantage of naming ports with an equate is that if, later in the design process, you decide to use a different port for the LED or the switch, only the equate has to be changed, not the program itself.
Please note that comments are very important. When you initially write a program, the tendancy is not to write much in the comment field because you're in a hurry. But if you have to come back to it a few weeks later, it's much easier to understand what you've written if you've taken the time to write good comments. Also good comments help in debugging.
To digress just a little here, an instruction like add B is a one byte instruction. In other words this instruction would end up inside the 8085 as one byte. Part of the byte is the opcode and the other part is which register is affected or used. The reason for this is that a prime concern in programming a micro is how may bytes the program will actually take up inside the micro, after it's been assembled. The idea is to cram as much as possible into as few bytes as possible. This is why implied addressing is used. It limits choices in the use of the instruction, you always have to use the accumulator as either the source or the destination, but it shrinks the size of the instruction, so that more instructions can fit inside the micro. This is a choice made by the maker of the micro, and is not up for discussion. It's a trade off of flexibility vs. size. That's why you'll see lots of instructions that use the accumulator. This is the best way to describe implied addressing.
In the case of an instruction like mvi A,1 ,two bytes are assembled. The first byte says that this is an move instruction and that the accumulator is the destination. The second byte is the immediate data itself. Thus we see that an instruction can have it’s data ‘next’ to it. It is transparent to the programmer where the bytes are actually stored in memory. Once we can ‘find’ it by an instruction is all that matters. We will get into this again, later.
Another form of addressing variables is called register indirect or just plain indirect addressing. This is a little more complicated. Here the address is held in a register, usually the H & L registers but sometimes the B & C or D & E. Since an address is 16 bits long, we need two registers (a register pair) to store an address. We will also get into this again, later.
Lastly, I want to explain something else about the assembler. The source file is what the above program, or any program that has been written, is referred to. It is the source for the assembler, or the file that is going to be read by the assembler to generate the object file (the object of the assembler) from. The object file is the file that will be download to the 8085 kit in the lab. They are two different files. One you've written with a text editor (the source or ASM file) and the other is created by the assembler (the object or OBJ file) when you assemble the source file. You use an assembler with the object in mind of generating a file to download to the micro, hence the name, object file.
I've left out some directives, for simplicities sake, that I need to mention now. One is the .org directive. It is the originate or origin directive. This tells the assembler at what address the first byte of assembled code is to be placed inside the 8085. It is the origin of the program or the beginning. Here's how this would look for our last example program:
.org 2000H ; begin using memory address 2000H
Well we've covered quite a lot in this lesson, and I hope you've gotten most of it. If not, I would suggest re-reading it until you do. I would also suggest that you print out all of these lessons so you can refer to them later. In the next lesson we will actually be assembling some programs and looking at the object files.

Address Decoding
As an assembly language programmer, you know that the CPU registers have no address. Instead, you specify them by name eg: A, B, C, etc.. As a result, it may seem confusing to you that to access an I/O port, you use an address, even though they may be thought of as similar to registers. CPU registers use the fastest (and most expensive) memory technology, then cache memory uses a slightly slower technology and then system RAM uses a slower and cheaper technology. Nevertheless, all are forms of memory. In fact, you could think of standard RAM as a large collection of slow registers. The difference is simply in the way that we name them.
You should also realize (especially if you have installed additional memory in your own computer) that RAM consists of multiple chips, each of which contains a number of memory locations. Each chip is physically just like every other chip. There is nothing about the chip itself that makes it hold a particular range of addresses. The locations on a single chips are linearly ordered, but there is no inherent ordering among the separate chips. The ordering comes from the way the chips are connected to the address bus. When you specify a particular address, the corresponding location exists only in one of those chips. In a very real sense, part of the address selects the correct chip (the upper part of the address), while the rest of the address selects the correct location on that chip. You can look at the low order bits as forming an offset from the first location on the chip to the correct location on the chip for the address you are specifying. The method that we use to select the correct location on the correct chip is called address decoding and we use the voltages carried on the wires of the address bus to accomplish the selection. Notice that it is critical that each address selects a unique location.
In additon to talking about memory addresses in memory space (or area), we also have an area the microprocessor treats slightly different called the port (I/O) space or area. On the 8085 CPU, we know the memory space is 64K bytes as there are 16 address lines. The port (I/O) space on the 8085 is 256 bytes as there are only 8 address lines used to select a port address. More on this later.
Each chip (whether it is a memory chip or a peripheral device chip) has an input called chip select ( ) or similar. To activate the chip, we must send a logic "0" (0 volts) to this input because it uses negative logic. If there is a logic "1" (+5 volts) on the wire connected to this input, the chip is inactive. Some chips also have an enable (EN) input. Chips of this type must receive a logic "1" on this input and a logic "0" on the input to be active. The fact that we can "turn on" (activate) or "turn off" (deactivate) a chip using signals like these allows us to select the correct chip for a particular address.
In order to see how this works in practice, we can design an address decoder for a very tiny memory, made up in part of "conventional RAM" and in part of I/O ports. You will recall from the beginning of the semester that the number of wires on the address bus determines the number of memory locations to which we have access. Conversely, the number of locations to which we need access determines the number of address lines we need. For this example, there will be sixteen 8-bit memory locations to which we want access. This means that we will need four address lines (24 = 16). Assume that we have eight memory locations in conventional memory and eight I/O ports. If we assume that each conventional memory chip contains four memory locations, we will need two chips or banks of memory. Assume the I/O ports are on eight separate chips, each with one register (in reality, peripheral devices typically have several registers each, but the concept is the same). Arbitrarily, we will say that the eight lowest addresses will be on the conventional memory chips and the eight highest addresses will correspond to the I/O ports on peripheral devices. First, we will specify all sixteen addresses in binary, so that we can see easily which address lines will have high voltage and which will have low voltage for any particular address.

The first thing we need to do is figure out how we can use the first eight patterns to activate the conventional memory chips and the second eight patterns to activate the I/O ports. We will use the EN input to enable the appropriate chips. Later, we will need to worry about the input, because both the EN and must receive appropriate inputs in order to activate a chip, but for now, we will just consider how to "enable" some of the chips. We need something that is common to all eight of the first set of patterns and that distinguishes them from the second set of eight patterns. If you look at the values of the A3 line, you can see that this line is always 0 for the first eight addresses and always 1 for the second set of eight addresses. We can use this line to provide the EN signal for both conventional memory and I/O ports (provided that the input also receives an appropriate input). Since A3 = 0 for the conventional memory addresses, we must invert it to obtain a 1 for the corresponding EN inputs. Since A3 = 1 for the I/O port addresses, we simply feed A3 directly to the EN inputs of the I/O ports.

Interrupts

Interrupts
In a typical computer system, the software can be divided into 3 possible groups. One is the Operating Loop, another is the Interrupt Service Routines, and the last is the BIOS/OS functions and subroutines. The Operating Loop is the main part of the system. It will usually end up being a sequence of calls to BIOS/OS subroutines, arranged in an order that accomplishes what we set out to do, with a little manipulation and data transfer in between. At the same time, at least it looks like it's happening at the same time, interrupts are being serviced as they happen. In the 8085, there are thirteen (13) possible events that can trigger an interrupt. Five of them are from external hardware interrupt inputs (TRAP, RST 7.5, 6.5, 5.5, and INTR), that can be from whatever hardware we've added to the 8085 that we deem to need servicing as soon as they happen. The remainder are software instructions that cause an interrupt when they are executed (RST 0 – 7).
To digress just a moment, there are two ways to service, or act on, events that happen in the system. One is to scan or poll them and the other is to use interrupts. Scanning is just what is sounds like. Each possible event is scanned in a sequence, one at a time. This is ok for things that don't require immediate action. Interrupts, on the other hand, cause the current process to be suspended temporarily and the event that caused the interrupt is serviced, or handled, immediately. The routine that is executed as a result of an interrupt is called the interrupt service routine (ISR), or recently, the interrupt handler routine.
In the 8085, as with any CPU that has interrupt capability, there is a method by which the interrupt gets serviced in a timely manner. When the interrupt occurs, and the current instruction that is being processed is finished, the address of the next instruction to be executed is pushed onto the Stack. Then a jump is made to a dedicated location where the ISR is located.. Some interrupts have their own vector, or unique location where it's service routine starts. These are hard coded into the 8085 and can't be changed (see below).
TRAP - has highest priority and cannot be masked or disabled. A rising-edge pulse will cause a jump to location 0024H.
RST 7.5- 2nd priority and can be masked or disabled. Rising-edge pulse will cause a jump to location 7.5 * 8 = 003CH.
This interrupt is latched internally and must be reset before it can be used again.
RST 6.5 – 3rd priority and can be masked or disabled. A high logic level will cause a jump to location 6.5 * 8 = 0034H.
RST 5.5 – 4th priority and can be masked or disabled. A high logic level will cause a jump to location 5.5 * 8 = 002CH.
INTR – 5th priority and can be masked or disabled. A high logic level will cause a jump to specific location as follows:
When the interrupt request (INTR) is made, the CPU first completes it’s current execution. Provided no other interrupts are pending, the CPU will take the INTA pin low thereby acknowledging the interrupt. It is up to the hardware device that first triggered the interrupt, to now place an 8-bit number on the data bus, as the CPU will then read whatever number it finds on that data bus and do the following: multiply it by 8 and jump to the resulting address location. Since the 8-bit data bus can hold any number from 00 – FFH (0 – 255) then this interrupt can actually jump you to any area of memory between 0*8 and 255*8 ie: 0000 and 07FFH ( a 2K space). N.B: This interrupt does not save the PC on the stack, like all other hardware and software interrupts!
You will notice that there isn't many locations between vector addresses. What is normally done is that at the start of each vector address, a jump instruction (3 bytes) is placed, that jumps to the actual start of the service routine which may be in RAM.. This way the service routines can be anywhere in program memory. The vector address jumps to the service routine. There is more than enough room between each vector address to put a jump instruction. Looking at the table above, there are at least 8 locations for each of the vectors except RST 5.5, 6.5, and 7.5. When actually writing the software, at address 0000h will be a jump instruction that jumps around the other vector locations.
Besides being able to disable/enable all of the interrupts at once (DI / EI) ie: except TRAP, there is a way to enable or disable them individually using the SIM instruction and also, check their status using RIM.
There are other things about interrupts that we will cover as they come up, but this lesson was to get you used to the idea of interrupts and what they're used for in a typical system. It’s similar to the scene where one is standing at a busy intersection waiting for the traffic light to change, when a person came up and tapped us on the shoulder and asked what time it was. It didn't stop us from going across the street, it just temporarily interrupted us long enough to tell them what time it was. This is the essence of interrupts. They interrupt normal program execution long enough to handle some event that has occurred in the system.
Polling, or scanning, is the other method used to handle events in the system. It is much slower than interrupts because the servicing of any single event has to wait its turn in line while other events are checked to see if they have occurred. There can be any number of polled events but a limited number of interrupt driven events. The choice of which method to use is determined by the speed at which the event must be handled.
The software interrupts are the instructions RST n, where n = 0 – 7. The value n is multiplied by 8 and the result forms an address that the program jumps to as it vector address ie: RST 4 would jump to location 4*8 = 32 (20H).

The STACK

The STACK
The stack is one of the most important things you must know when programming. Think of the stack as a deck of cards. When you put a card on the deck, it will be the top card. Then you put another card, then another. When you remove the cards, you remove them backwards, the last card first and so on. The stack works the same way, you put (push) words (addresses or register pairs) on the stack and then remove (pop) them backwards. That's called LIFO, Last In First Out.
The 8085 uses a 16 bit register to know where the stack top is located, and that register is called the SP (Stack Pointer). There are instructions that allow you to modify it’s contents but you should NOT change the contents of that register if you don't know what you're doing!
PUSH & POP
As you may have guessed, push and pop “pushes” bytes on the stack and then takes them off. When you push something, the stack counter will decrease with 2 (the stack "grows" down, from higher addresses to lower) and then the register pair is loaded onto the stack. When you pop, the register pair is first lifted of the stack, and then SP increases by 2.
N.B: Push and Pop only operate on words (2 bytes ie: 16 bits).
You can push (and pop) all register pairs: BC, DE, HL and PSW (Register A and Flags). When you pop PSW, remember that all flags may be changed. You can't push an immediate value. If you want, you'll have to load a register pair with the value and then push it. Perhaps it's worth noting that when you push something, the contents of the registers will still be the same; they won't be erased or something. Also, if you push DE, you can pop it back as HL (you don't have to pop it back to the same register where you got it from).
The stack is also updated when you CALL and RETurn from subroutines. The PC (program counter which points at the next instruction to be executed) is pushed to the stack and the calling address is loaded into PC. When returning, the PC is loaded with the word popped from the top of the stack (TOS).
So, when is this useful? It's almost always used when you call subroutines. For example, you have an often used value stored in HL. You have to call a subroutine that you know will destroy HL (with destroy I mean that HL will be changed to another value, which you perhaps don't know). Instead of first saving HL in a memory location and then loading it back after the subroutine, you can push HL before calling and directly after the calling pop it back. Of course, it's often better to use the pushes and pops inside the subroutine. All registers you know will be changed are often pushed in the beginning of a subroutine and then popped at the end, in reverse order! Don't forget - last in first out. If you want to only push one 8 bit register, you still have to push it's "friend". Therefore, be aware that if you want to store away D with pushing and popping, remember that E will also be changed back to what it was before. In those cases, if you don't want that to happen, you should try first to change register (try to store the information in E in another register if you can) or else you have to store it in a temporary variable.
Before executing a program, you should keep track of your pushes and pops, since they are responsible for 99% of all computer crashes! For example, if you push HL and then forget to pop it back, the next RET instruction will cause a jump to HL, which can be anywhere in the ROM/RAM and the ccomputer will crash. Note however, it’s also a way to jump to the location stored in HL, but then you should really use the JMP instruction, to do the same thing.
Push and pop doesn't change any flags, so you can use them between a compare and jump instructions, depending on a condition, which is often very useful.

The 8085 Instruction Set

The 8085 Instruction Set

Instructions can be categorized according to their method of addressing the hardware registers and/or memory.

Implied Addressing:
The addressing mode of certain instructions is implied by the instruction’s function. For example, the STC (set carry flag) instruction deals only with the carry flag, the DAA (decimal adjust accumulator) instruction deals with the accumulator.

Register Addressing:
Quite a large set of instructions call for register addressing. With these instructions, you must specify one of the registers A through E, H or L as well as the operation code. With these instructions, the accumulator is implied as a second operand. For example, the instruction CMP E may be interpreted as 'compare the contents of the E register with the contents of the accumulator.

Most of the instructions that use register addressing deal with
8-bit values. However, a few of these instructions deal with 16-bit register pairs. For example, the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers.

Immediate Addressing:
Instructions that use immediate addressing have data assembled as a part of the instruction itself. For example, the instruction CPI 'C' may be interpreted as ‘compare the contents of the accumulator with the letter C. When assembled, this instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal representation for the letter C. When this instruction is executed, the processor fetches the first instruction byte and determines that it must fetch one more byte. The processor fetches the next byte into one of its internal registers and then performs the compare operation.

Notice that the names of the immediate instructions indicate that they use immediate data. Thus, the name of an add instruction is ADD; the name of an add immediate instruction is ADI.

All but two of the immediate instructions uses the accumulator as an implied operand, as in the CPI instruction shown previously. The MVI (move immediate) instruction can move its immediate data to any of the working registers including the accumulator or to memory. Thus, the instruction MVI D, OFFH moves the hexadecimal
value FF to the D register.

The LXI instruction (load register pair immediate) is even more unusual in that its immediate data is a 16-bit value. This instruction is commonly used to load addresses into a register pair. As mentioned previously, your program must initialize the stack pointer; LXI is the instruction most commonly used for this purpose. For example, the instruction LXI SP,3OFFH loads the stack pointer with the hexadecimal value 30FF.


Direct Addressing:
Jump instructions include a 16-bit address as part of the instruction. For example, the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value 1000H.

Instructions that include a direct address require three bytes of storage: one for the instruction code, and two for the 16-bit address

Register Indirect Addressing:
Register indirect instructions reference memory via a register pair. Thus, the instruction MOV M,C moves the contents of the C register into the memory address stored in the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair.

Combined Addressing Modes:
Some instructions use a combination of addressing modes. A CALL instruction, for example, combines direct addressing and register indirect addressing. The direct address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL instruction pushes the current contents of the program counter into the memory location specified by the stack pointer.

Timing Effects of Addressing Modes:
Addressing modes affect both the amount of time required for executing an instruction and the amount of memory required for its storage. For example, instructions that use implied or register addressing, execute very quickly since they deal directly with the processor’s hardware or with data already present in hardware registers. Most important, however is that the entire instruction can be fetched with a single memory access. The number of memory accesses required is the single greatest factor in determining execution timing. More memory accesses therefore require more execution time. A CALL instruction for example, requires five memory accesses: three to access the entire instruction and two more to push the contents of the program counter onto the stack.

The processor can access memory once during each processor cycle. Each cycle comprises a variable number of states. (See below and the appendix of “USING THE SDK-85 MICROPROCESSOR TRAINER”). The length of a state depends on the clock frequency specified for your system, and may range from 480 nanoseconds to 2 microseconds. Thus, the timing for a four state instruction may range from 1.920 microseconds through 8 microseconds. (The 8085 have a maximum clock frequency of 5 MHz and therefore a minimum state length of 200 nanoseconds.)

Instruction Naming Conventions:
The mnemonics assigned to the instructions are designed to indicate the function of the instruction. The instruc­tions fall into the following functional categories:

Data Transfer Croup:
The data transfer instructions move data between registers or between memory and registers.

MOV Move
MVI Move Immediate
LDA Load Accumulator Directly from Memory
STA Store Accumulator Directly in Memory
LHLD Load H & L Registers Directly from Memory
SHLD Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits);

LXI Load Register Pair with Immediate data
LDAX Load Accumulator from Address in Register Pair
STAX Store Accumulator in Address in Register Pair
XCHG Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L

Arithmetic Group:
The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.

ADD Add to Accumulator
ADI Add Immediate Data to Accumulator
ADC Add to Accumulator Using Carry Flag
ACI Add Immediate data to Accumulator Using Carry
SUB Subtract from Accumulator
SUI Subtract Immediate Data from Accumulator
SBB Subtract from Accumulator Using Borrow (Carry) Flag
SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag
INR Increment Specified Byte by One
DCR Decrement Specified Byte by One
INX Increment Register Pair by One
DCX Decrement Register Pair by One
DAD Double Register Add; Add Content of Register
Pair to H & L Register Pair

Logical Group:
This group performs logical (Boolean) operations on data in registers and memory and on condition flags.

The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or OFF.

ANA Logical AND with Accumulator
ANI Logical AND with Accumulator Using Immediate Data
ORA Logical OR with Accumulator
OR Logical OR with Accumulator Using Immediate Data
XRA Exclusive Logical OR with Accumulator
XRI Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;

CMP Compare
CPI Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position to the left or right:

RLC Rotate Accumulator Left
RRC Rotate Accumulator Right
RAL Rotate Left Through Carry
RAR Rotate Right Through Carry

Complement and carry flag instructions:

CMA Complement Accumulator
CMC Complement Carry Flag
STC Set Carry Flag

Branch Group:
The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as follows:

JMP Jump
CALL Call
RET Return

Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows:

NZ Not Zero (Z = 0)
Z Zero (Z = 1)
NC No Carry (C = 0)
C Carry (C = 1)
PO Parity Odd (P = 0)
PE Parity Even (P = 1)
P Plus (S = 0)
M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns
C CC RC (Carry)
INC CNC RNC (No Carry)
JZ CZ RZ (Zero)
JNZ CNZ RNZ (Not Zero)
JP CP RP (Plus)
JM CM RM (Minus)
JPE CPE RPE (Parity Even)
JP0 CPO RPO (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program counter:

PCHL Move H & L to Program Counter
RST Special Restart Instruction Used
with Interrupts

Stack I/O, and Machine Control Instructions:
The following instructions affect the Stack and/or Stack Pointer:

PUSH Push Two bytes of Data onto the Stack
POP Pop Two Bytes of Data off the Stack
XTHL Exchange Top of Stack with H & L
SPHL Move content of H & L to Stack Pointer

The I/0 instructions are as follows:

IN Initiate Input Operation
OUT Initiate Output Operation

The Machine Control instructions are as follows:
EI Enable Interrupt System
DI Disable Interrupt System
HLT Halt
NOP No Operation

General Description about 8085

GENERAL DESCRIPTION
The Intel 8085 microprocessor is an NMOS 8-bit device. Sixteen address bits provide access to 65,536 bytes of 8 bits each. Eight bi-directional data lines provide access to a system data bus. Control is provided by a variety of lines which support memory and I/O interfacing, and a flexible interrupt system. The 8085 provides an upward mobility in design from the 8080 by supporting all of the 8080’s instruction set and interrupt capabilities. At the same time, it provides cleaner designs by virtue of a greater on-device component density, and by requiring only a 5 volt supply. In addition, the 8085 is available in two clock speeds.
The 8085 comes in two models, the 8085A and the 8085A-2. The 8085A expects a main clock frequency of 3 MHz, while the 8085A-2 expects a main clock frequency of 5 MHz. In both cases, the clock is a single phase square wave. This single clock is generated within the 8085 itself, requiring only a crystal externally. This eliminates the need for an external clock generator device. In all other respects, the A and A-2 devices are identical.
The 8085 supports the interrupt structure of the 8080, including the RST instruction and the eight vectors. It extends these by the addition of four more interrupts, each with their own pins, three of which are maskable, and which use vector areas between the existing ones of the 8080. The 8085 is adaptable for use with the 8259 Priority Interrupt Controller, a programmable device. It is possible, upon an interrupt from this device, to jam either a RST instruction onto the data lines, or a CALL instruction to any location in RAM directly.
The 8085 has two pins dedicated to the generation or reception of serial data. While these do not constitute a complete serial I/O system, they do allow the MP to send and receive serial bits, albeit with a large software overhead. The 8085 therefore finds itself useful as a complete control device for remote control applications.
The 8085 supports the entire 8080 instruction set. In addition, two new instructions are added. These instructions permit software control over the extended interrupt capabilities of the ‘85, by making the new interrupts both maskable and interrogatable. The masks can be set, examined, etc.. The same instructions also allow investigation of the serial input line, and generation of conditions on the serial output line.
Unlike the 8080 which had discrete pins for the address and data busses, the 8085 make use of multiplexing of the lower 8 bits of the address with the data bits on the same 8 pins. This requires that the external circuitry be able to catch and hold the A0-A7 lines for later use. The upper 8 bits of the address have their own pins, however. Three primary control bus lines allow the device to identify whether the cycle in progress is for RAM or I/O, and whether it is a Read or a Write. Two status pins are provided, to allow advance knowledge of certain events in multiprocessor applications.
The internal timing of the device makes use of machine cycles in which, in almost every case, a bus cycle is involved. Each machine cycle consists of several T-states, which are defined by the clock input signal. Thus, many clock cycles are needed to effect one complete instruction. The 8085 has many new support devices to ease design work. These include the 8259 Programmable Interrupt controller, the 8202 Dynamic RAM controller, plus several new I/O devices with various amounts of RAM, ROM, parallel I/O, and timer-counters. The general approach was to make the device as compatible with the Multibus architecture as possible.

Data Flow in 8085

DATA FLOW

Locate the dataflow diagram in your reference manual. The dataflow of the 8085 is made up of the following units:
A General Purpose Register Array, most of which is accessible by the programmer, and which forms the essential data manipulation ability of the system;
An address generation system consisting of the Program Counter, Stack Pointer, address latches, and incrementer/decrementer. Two additional 8-bit latches are provided. The first, labeled Address Buffer, provides the upper byte of an address to the system address bus in a straight-through manner. The second, labeled Data/Address Buffer, provides the lower byte of the address early in a machine cycle; it is used later in the cycle to provide or accept an 8-bit data byte from the internal data bus of the MP to the system data bus, or from the system data bus to the MP’s data bus. This buffer therefore provides the AD0 - AD7 multiplexed address/data function mentioned above.
A mathematical and logical subsystem composed of the Arithmetic Logic Unit (ALU) and asS0ciated registers, which handle the math and logic functions of the machine;
An Instruction Register and decoder system which interpret the programmer’s instructions and implement them via nanocode;
A timing and control package which provides the bodily functions of power and clock circuits, and handles the wait, interrupt, and hold functions of the system;
An 8-bit internal data bus, which provides the data path between functional elements, and to the outside world via the Address/Data Buffer;
Interrupt control interfacing which provides both the standard 8080 interrupt structure, and 4 new interrupts which are maskable under special program controls, these last via the internal data bus;
Two serial data lines, Serial Input Data and Serial Output Data, which feed the internal data bus directly, and are serviced as part of the interrupt control structure mentioned above.
The General Purpose Register Array contains the B, C, D, E, H, and L registers, each 8 bits wide. The B and C, D and E, and H and L registers may be grouped into 16-bit register pairs. The H&L register pair may be used to store indirect addresses.
The array also contains the Program Counter (PC) and Stack Pointer (SP). These 16-bit registers contain the address of the next instruction part to be fetched, and the address of the top of the stack, respectively.
The GPR array also includes an Address Latch/Incrementer-Decrementer circuit, to make the address next required on the system address bus available to it, and to increment or decrement addresses or register contents as required.
The mathematical and logical function of the system are provided by an 8-bit Arithmetic-Logic Unit (ALU), which accepts two 8-bit arguments and generates an 8-bit result. It is fed by an Accumulator register and a Temporary register, both 8 bits wide; the result returns to the internal data bus for distribution. The ALU also has a Condition Flags register, for the storage of the conditions under which an operation ended, which may be used by following instructions. In all cases, the ALU, Accumulator, and Condition Flags function exactly as in the 8080.
The Instruction Register and Instruction Decoder accept the incoming byte from the data bus during the first machine cycle of an instruction, and interpret it by controlling the internal reS0urces of the MP as S0urces and destinations for bits and bytes. The 8085 is nanoprogram-controlled.
Acting under the direction of the instructions, the Timing and Control section of the 8085 generates the necessary timing pulses to synchronize their execution. The 8085 has its own internal oscillator, which requires only an external crystal to generate the clocks. The internal workings of the ‘85 require only a single phase clock, with a 50% duty cycle, which minimizes system timing requirements. This clock is made available to the outside world to allow external functions to be synchronized to the MP’s cycles.
Ready - Wait functions are provided in the ‘85. If a memory circuit’s response time is such that the MP will expect data before the RAM is ready to respond, the memory subsystem may request a Wait State (Tw) by pulling the Ready line low. This must be done prior to a certain point in the machine cycle. This function is important because the ‘85 is designed to work at 3 MHz, decreasing the time within which the RAM may respond.
The Timing and Control section of the ‘85 also provides several native signals, both inbound and outbound, which interface with the external world, and provide control signals and timing to the three-bus architecture. This makes way, then, for the multiplexing of the address and data on the AD0-AD7 lines. These lines include /Read, /Write, and I-O/M, which indicate whether the function to be performed is a input or an output, and whether it is addressed to memory or an I/O device; Address Latch Enable and two status lines so and S1, which advise the external world of the status of each machine cycle of the 8085; Hold and Hold Acknowledge, which allow the external I/O to ask for and receive a DMA cycle; and Reset In and Out, which provide the reset.
The 8085 also supports the interrupt structure of the 8080, with the Interrupt and Interrupt Acknowledge lines. In the ‘85, however, these lines are made available to the internal data bus of the MP instead of being connected directly to the Timing and Control logic. The external circuits see the operation of them as the same, however. In addition, four more interrupts are available, also connected to the data bus inside the MP, but these are under special software control with two OP codes. The reason for the placement of the interrupts onto the data bus will be shown later.
Two I/O lines are provided on the ‘85 which allow a single bit to be tested or presented directly by the MP. The Serial Data In (SID) and Serial Data Out (SOD) lines may be sensed or driven under program control via the same two instructions included for the new interrupt scheme. They allow the MP to treat them as either true serial data I/O, if programmed timing loops are included, or as simple single bit test or control ports for the sensing or control of external events.

Interfacing The 8085

INTERFACING THE 8085

A brief description of the signals between the 8085 and the outside world follows. Refer to the reference manual for pin-outs and details.
ADDRESS LINES A8 - A15: These tristate lines are outbound only. They provide the upper 8 bits of the 16-bit-wide address which identifies one unique 8-bit byte within the MP’s address space, or the 8-bit address of an I/O device. Sixteen address lines provide an address space of 65,536 locations.
ADDRESS-DATA LINES AD0 - AD7: These tristate lines may by either inbound or outbound. They provide a multiplexing between the lower 8 bits of the 16-bit-wide address early in a machine cycle and 8 data bits later in the cycle. When containing addresses, these lines are outbound only; when containing data, they may be either inbound or outbound, depending upon the nature of the machine cycle. They also will contain the 8 bits of an I/O device address during an I/O operation.
ADDRESS LATCH ENABLE (ALE): This signal appears outbound early in a machine cycle to advise the external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a memory address. It should be used to clock a catch-and-hold circuit such as a 74LS245 or 74LS373, so that the full address will be available to the system for the rest of the machine cycle. The documentation states that the falling edge of ALE is the point at which the signals on the AD lines, as well as the so, S1, and I-O/M lines (below) will be stable and may be taken by the external circuitry.
STATUS LINES so, S1, & I-O/M: These three status lines serve to indicate the general status of the processor with respect to what function the MP will perform during the machine cycle. The so and S1 lines are made available for circuits which need advanced warning of the ensuing operation, such as very slow RAM or other specialized devices. The system may not normally need to monitor these lines. The I-O/M line approximates in one line what the so and S1 lines do in two. It indicates whether the operation will be directed toward memory (line is low), or toward I/O (line is high). Refer to the manual for a full explanation.
READ & WRITE (/RD & /WR): These lines indicate which direction the MP expects to pass data between itself and the external data bus. Read indicates that the MP is expecting data to be fed to it; Write indicates that the MP is going to send data away from itself. These lines also serve to time the event, as well as identify its direction.
READY: This is an input line which may be used as a signal from external RAM that a wait state is needed, since the RAM is not able to provide the data or accept it in the time allowed by the MP. The negation of Ready, by being pulled low, will cause the 8085 to enter wait states. See the timing diagrams for critical timing.
HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA): These lines provide the 8085 with a DMA capability by allowing another processor on the same system buses to request control of the buses. Upon receipt of HOLD, the ‘ 85 will tristate its address, data, and certain control lines, then generate HLDA. This signals the other processor that it may proceed. The ‘85 will remain off the buses until HOLD is negated.
INTERRUPT & INTERRUPT ACKNOWLEDGE (INTR & INTA): These lines provide a vectored interrupt capability to the 8085. Upon receipt of INTR, the ‘85 will complete the instruction in process, then generate INTA as it enters the next machine cycle. The interrupting device will jam a Restart (RST) instruction onto the data bus, which the ‘85 uses to locate an interrupt vector in low RAM.
RST 5.5, 6.5, 7.5: These three lines are additional interrupt lines which generate an automatic Restart, without jamming, to vectors in low RAM which are between those used by the normal INTR instruction. The 5.5 line, for example, will cause an automatic restart to a 4-byte vector located between 5 and 6 of the normal vectors used by INTR. These lines have priority over the INTR line, and each other. They also have certain electrical characteristics for assertion, and may be masked off or on by software. More on the 8085’s interrupts later.
TRAP: This is an unmaskable interrupt with a fixed vector in low RAM. See the interrupt discussion later in the notes.
RESET IN & RESET OUT: These lines provide for both MP and system reset. The reset circuitry in the 8224, used with the 8080, has been brought inside the MP. The RESET IN line is generated asynchronously by some sort of external circuit, such as an RC network or Reset switch. Upon receipt of this signal, the ‘85 will internally synchronize the Reset with the clock of the processor, then generate RESET OUT for other devices in the system. See the reference manual for details.
X1 & X2: These two pins provide connection for an external frequency determining circuit to feed the 8085’s clock. This is normally a crystal, although other resonant circuits may be used. X1 alone may be used as a single input from an external oscillator. The internal oscillator of the ‘85 will divide the frequency by two for the system clock.
CLOCK (CLK): This line provides a system clock signal to external circuits which need to be in synchronization with the MP.
SERIAL INPUT DATA & SERIAL OUTPUT DATA (SID & SOD): These two lines provide for a single serial input or output line to/from the 8085. These lines are brought into the device as D7, and may be tested or set by the Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions. These two instructions also have control over the mask which controls the RST 5.5, 6.5, and 7.5, and TRAP, interrupts. The SID and SOD lines are simple single bit I/O lines; any timing required to provide external communication via them must be provided by the software.
· Vcc & Vss: These are the power connections for +5 volts and ground, respectively.

The Processor Cycle of 8085

THE PROCESSOR CYCLE

The time required by the 8085 to fetch and execute one machine language instruction is defined as an Instruction Cycle. As in the 8080, the instructions may be of different complexities, with the result that the more complicated instructions take longer to execute. The 8085’s method of instruction execution inside the MP is more organized, however, and so the time required to execute any instruction is more predictable and more regular.
Each instruction is divided into one to five Machine Cycles. Each machine cycle is essentially the result of the need, by the instruction being executed, to access the RAM. The shortest instruction would require just one machine cycle, in which the instruction itself is obtained from RAM. The longest, of five machine cycles, would consist of five RAM accesses, the first to obtain the instruction byte itself, and the remaining four to be divided into fetching and saving other bytes. For example, cycles numbers 2 & 3 may be needed to fetch two more bytes of an address, while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM.
The type of machine cycle being executed is specified by the status lines I-O/M, S0, and S1, and the control lines /RD, /WR, and /INTA. These six lines can define seven different machine cycle types as follows. Refer to the chart in the manual which defines the bit patterns of each.
OP CODE FETCH: This is the first machine cycle of any instruction. It is defined with S0 and S1 asserted high, and I-O/M and /RD low. It is a read cycle from RAM to obtain an instruction byte.
MEMORY READ: This is a normal read cycle of any byte except the OP code. It is defined with S0 and S1 set to 0, 1 respectively, and I-O/M and /RD low. It is a read cycle from RAM to obtain a data or address byte.
MEMORY WRITE: This is a normal write cycle to memory. It is defined with S0 and S1 set to 1, 0 respectively, and I-O/M and /WR low. It is a write cycle to RAM to store one byte in the specified address.
I/O READ: This is a normal read cycle from an I/O device. It is defined with S0 and S1 set to 0, 1 respectively, and with I-O/M high and /RD low. It is a read cycle which will bring one byte into the MP from the input device specified.
I/O WRITE: This is a normal write cycle to an I/O device. It is defined with S0 and S1 set to 1, 0 respectively, and with I-O/M high and /WR low. It is a write cycle which will send one byte outbound from the MP to the specified output device.
INTERRUPT ACKNOWLEDGE: This is a response to an interrupt request applied to the MP via the INTR line. It is defined with S0 and S1 set to 1, 1 respectively, I-O/M set high, and both /RD and /WR also high. The Interrupt Acknowledge pin is also held to a low asserted level. l It is neither a read nor write cycle, although the interrupting device will jam an interrupt vector onto the D0-D7 lines on the next machine cycle.
BUS IDLE: This is an idle cycle in which no specific bus activity is defined. It occurs under three differently defined conditions:
Double Add Instruction (DAD): This instruction requires enough execution time to merit its own Idle cycle. It is defined with S0 and S1 set to 0, 1 respectively, I-O/M set low, and neither /RD nor /WR asserted (both high). Since neither a read nor a write are specified, no bus action takes place.
Acknowledge of Restart or Trap: This idle cycle allows time for the ‘85 to cope with a RST or Trap interrupt request. All bits are held high.
Halt: This idle cycle indicates that the MP has executed a Halt instruction. The I-O/M, /RD, and /WR lines are all tristated, which would allow them to be controlled by other devices. INTA is held inactive, but not tristated. The Hold line is really the proper one to use for DMA or multiple processors.
Each of the machine cycles defined above, during which an access of a RAM address or an I/O device is made (except the idle cycles), is further divided into T-states. Each T-state, for an ‘85 with a 3 MHz clock, will be about 333 nanoseconds in length. The first machine cycle, during which the OP code is being fetched, will be either 4 or 6 T-states in length. Whether 4 or 6 T-states are used depends upon whether the instruction needs further information from RAM, or whether it can be executed to completion straight away If multiple accesses are needed, the cycle will be 4 states long; if the execution can run to completion, 6 states are required. (Remember that the ‘85 is running with a faster clock, so that less time per T-state is available.)
The number of T-states for the second and succeeding machine cycles will always be 3 for normal instructions. There are two exceptions to this general rule. The first exception is in response to the request for wait states from an external device which has pulled the Ready line low. This will cause the ‘85 to insert one or more Tw states between T2 and T3, as in the 8080. The second exception is when the ‘85 is placed into the Hold condition in response to a signal from an outside device applied to the Hold line. This will be an indeterminate amount of time during which the external device will be performing a DMA function.
The documentation includes a small chart which specifies the actions of the major signals of the ‘85 during each of the 10 possible types of T-states. It may be summarized as follows:
T1 STATE: This state is the first of any machine cycle. The chart shows that S0-S1 lines, I-O/M, A8-A15, and AD0-AD7 contains whatever would be appropriate for the type of instruction being executed. (The "X" in the chart is defined as "unspecified", which translates to "whatever is normal".) The S0-S1 and I-O/M lines will define, at this early point in the machine cycle, whether the MP is attempting to address a RAM location or an I/O device. The address lines will identify the location or I/O device to be dealt with. The Address Latch Enable (ALE) line will allow some sort of external circuitry to catch and hold the contents of the AD0-AD7 lines to be used as the low byte of the address.Note that while the S0 and S1 lines may safely be ignored for general purposes, they are provided to allow the engineer to obtain an advanced warning of the type of function that will be specified during T2, i.e., a read or a write. An engineer can monitor this lines with circuitry of his own to generate his own "Early Read" or "Early Write" if he needs it for slow peripheral devices or devices. The /RD, /WR, and /INTA lines are all negated at this time. Since the AD0-AD7 lines are being used to present an address byte, it would be inappropriate to move data on the data bus; besides, it’s too early to do so. It’s also too early for /INTA. ALE, however, is asserted, since this is the time that the AD0-AD7 contents will contain the lower address byte, which must be caught and held outside the ‘85 for use by the following T-states.
T2 STATE: The chart indicates that all lines except ALE (which will be inactive for the rest of the machine cycle) will assume the proper level for the type of instruction in progress. The address lines retain the bit pattern selecting one byte from RAM or an I/O device; the AD0-AD7 lines will now prepare to either accept or present a data byte (they are in a state of transition during T2); I-O/M and the S0, S1 lines are still displaying the original settings of T1. Either /RD or /WR will assert during T2, to indicate the nature of the data transaction. /INTA will assert at T2 if an interrupt cycle has started.
WAIT STATE: If the Ready line was negated during T2, a Tw is inserted to allow the external circuitry more time to prepare for data transmission. A specific point in T2 is defined, after which a late negation of Ready will not cause the Tw to be inserted. This corresponds to the same actions in the 8080 device. All signals set up during T2 will remain constant during Tw.
T3 STATE: All lines set up during T2 will remain the same in T3, except the AD0-AD7 lines, which will be conducting data either into or out of the 8085. At the end of T3, the /RD or /WR line will negate to indicate the end of the active function. This will cause the data byte standing on AD0-AD7 to disappear.
T4 - T6 STATES: These states are required for time to permit the 8085 to continue processing internally. No bus actions are required. The S0 & S1 lines are both asserted, while I-O/M is negated, which specifies that the ‘85 is involved in an 0P code fetch. Since T4 through T6 will exist only on the first machine cycle of an instruction, this corresponds correctly with the Machine Cycle chart. The AD0-AD7 lines are tristated; the A8-A15 retain their original setting; the /RD, /WR, and INTA lines are all negated.
In addition to the T-states described above, the chart also indicates the conditions during states involved in Resets, Halts, and Holds. It must be kept in mind that during any of these, the MP clocks are still running, and the ‘85 is alive inside; it has simply shut itself off the buses to allow external events to occur. These states tristate the address, AD, I-O/M, /RD, and /WR lines to allow external devices to control them. The other lines are held at inactive levels except the S0 & S1 lines, which do indicate what type of machine cycle the system is in, i.e., whether it is a Reset, Hold, or Halt.

Timing diagrams & Introduction to instruction set

TIMING DIAGRAMS
Locate the figure in the Intel documentation labeled 8085A Basic System Timing. This diagram illustrates the events in an instruction of three machine cycles. The M1 cycle is four states long, and the events at each state are shown. Notice particularly the operation of the AD0-AD7 lines, which provide the lower address byte during T1, followed by data during the later part of T2 and all of T3. Observe that the ALE line corresponds to the presentation of this low address byte. Note also that in a machine cycle in which data is going to be read, the AD lines actually capture the incoming byte during the middle of T3, and may drift around in the later part of T2. Compare this to the case of a write, in which the ‘85 presents the data byte to be written early in T2, and holds it constant until the end of T3.
Several other timing diagrams are included in the documentation which illustrate the details of each different cycle that the ‘85 can perform. These all conform nicely to the Basic System Timing diagram, with the addition of wait states, and of specific lines to perform specific functions. The Instructor will discuss these with you.
HOLD AND HALT STATES
The 8085 has provisions for the execution of a Halt instruction, which causes the system to go into T-halt states. During this time, the ‘85 is simply waiting for something to occur. There are three ways out of a Halt: A Reset, a Hold Request, and an enabled interrupt. If a Hold Request occurs during a Halt, the ‘85 will honor it by going into T-hold cycles as long as the Hold line remains asserted; it will return to the halt condition when Hold negates. If an interrupt occurs during a halt, the MP will go into an interrupt cycle if the interrupt was enabled; it will be ignored if it was not enabled. An enabled interrupt during a hold state will have to wait until the hold clears before being given control of the system. Two diagrams are included in the documentation to indicate the various combinations of hold, halt, and interrupts.
INSTRUCTION SET
The instruction set of the 8085 is identical to that of the 8080, with the exception of the addition of two instructions, RIM and SIM. The definitions of the OP codes, how they work, the operation of the condition flags, addressing modes, and the use of the H and L register pair for indirect addressing are all identical between the two processors.
The Intel documentation shows many symbols used to describe the functions and relations of parts of instructions. These include the use of lower case letters, especially the "r", to indicate a register, "rp" to indicate a register pair, "addr" to indicate an address, "data" to indicate an 8-bit data byte, "data 16" to indicate a 16-bit data word, "rh" and "rl" to indicate the high-order register and the low-order register of a register pair, respectively, and the use of some upper case, such as "PC" for program counter and "SP" for stack pointer. Many graphics symbols are used, and the instructor will now discuss them with you at length, using the documentation as reference. Be sure you understand them before proceeding.

Flag Register & Instruction Organization

FLAG REGISTER
The Status Flags of the 8080 and 8085 are single bits which indicate the logical conditions that existed as a result of the execution of the instruction just completed. This allows instructions following to act accordingly, such as a branch as a result of two values comparing equal. The flags are:
ZERO FLAG: This flag is set to a 1 by the instruction just ending if the A Register contains a result of all 0’s. Besides the obvious mathematical applications, this is useful in determining equality in a compare operation (a value subtracted from a second value with an answer of 0), or in logical AND or OR operations where the result left the A Register with no bit set to a 1 (the AND was not satisfied). If any bits were left set to a 1 in the A Register, the flag will be reset to a 0 condition.
SIGN FLAG: This flag is set to a 1 by the instruction just ending if the leftmost, or highest order, bit of the A Register is set to a 1. The leftmost bit of a byte in signed arithmetic is the sign bit, and will be 0 if the value in the lower seven bits is positive, and 1 if the value is negative.
PARITY FLAG: This flag is set to a 1 by the instruction just ending if the A Register is left with an even number of bits set on, i.e., in even parity. If the number of bits in the A Register is odd, the bit is left off. This may be useful in I/O operations with serial devices, or anyplace that error checking is to be done.
CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry out of the leftmost bit occurred during the execution of the instruction. An example would be the addition of two 8-bit numbers whose sum was 9 bits long. The 9th bit would be lost, yielding an erroneous answer if the carry bit was not captured and held by this flag. This flag is also set if a borrow occurred during a subtraction or a compare operation.
AUXILIARY CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry occurred from bit 3 to bit 4 of the A Register during the instruction’s execution. Because of the relationships of decimal in pure BCD to hexadecimal coding, it is possible to bring BCD values directly into the A Register and perform mathematical operations on them. The result, however, will be as if two hex characters are being processed. If the result must be returned to the program as BCD rather than as hex, the Decimal Adjust Accumulator (DAA) instruction can make that translation; the Auxiliary Carry Flag is provided to assist in this operation.
INSTRUCTION ORGANIZATION
The 8085’s instructions are made up of bytes. In microprocessor parlance, a byte is described as 8 contiguous binary bits treated as a unit. The least significant bit is on the right, and is labeled Bit 0. The most significant bit is on the left, and is Bit 7. Thus, the machine coding is "origin zero", unless noted otherwise. Note also that there is no parity bit, or provision for it, as would be found in larger systems.
The 8085’s instructions are either one, two, or three bytes long. In all cases, the first byte contains the essential information, such as the OP code. The second and third bytes, if included, provide operand information that won’t fit in the first byte.
A close look at the first byte of each instruction will reveal a very great similarity between the 8085’s instruction format and that of the PDP11 system by DEC. In many instances, the description of the instructions in the Intel documentation specifies that certain bits of the first byte (#2,1,0) be designated as the "source" operand, and others (#5,4,3) as the "destination" operand. In this manner, all of the major functional units available to the programmer are encoded into three bits, according to the chart below:
DDD or SSS
Register Name
111
A
000
B
001
C
010
D
011
E
100
H
101
L
Similarly, the registers may be defined as register pairs, and two bits within the first byte may then be used to define these:
RP Bits
Register Pair
00
B-C
01
D-E
10
H-L
11
SP
The similarity between PDP11 and 8085 instruction sets is interesting, but by no means rigid. Many differences exist, primarily due to the difference between the 8- and 16-bit architectures.

Adressing Modes & Branch Instruction Types

ADDRESSING MODES
The 8085 provides four different modes for addressing data, either in its registers or in memory. These are described below:
DIRECT MODE - This mode creates instructions three bytes long. The first byte contains the operation to be performed. The second and third bytes contain the address in memory where the data byte may be found. Thus, the instruction directly specifies the absolute location of the data. Note that the second byte of the instruction contains the low order byte of the address, while the third byte contains the high order byte of the address. This illustrates the inverse addressing of the device.
REGISTER MODE - This mode results in single-byte instructions. The byte contains bits which specify a register or register pair in which the data is located.
REGISTER INDIRECT MODE - This mode results in single-byte instructions. The byte contains bits which specify a register pair, which in turn contains the address of the data in memory. Thus, the instruction indirectly specifies the address of the data by referring to a register pair for the absolute address. Note that the high order byte of the address is stored in the leftmost register of the pair, while the low order byte of the address is stored in the rightmost register of the pair. The address 3000H, therefore, would be stored in the HL register pair as 30 in H, and 00 in L.
IMMEDIATE MODE - This mode results in a two or three byte instruction. The first byte contains the instruction itself. The second and third bytes contain the immediate data, either as a single 8-bit value, or as a 16-bit value. If the 16-bit value is used, the bytes are reversed as discussed previously, with the second byte containing the low order byte, and the third byte containing the high order byte.

BRANCH INSTRUCTION TYPES
Normal execution of instructions is in a straight line. Branch instructions are available to alter the course of execution flow. These instructions can specify the address of the next instruction to be executed, if it is not the one immediately following the branch, in two ways:
DIRECT BRANCH - In this mode, the branch contains the address to be used, if the branch occurs, as two bytes following the instruction byte. The second byte contains the low order byte, while the third byte contains the high order byte.
REGISTER INDIRECT BRANCH - In this mode, the branch specifies a register pair which will contain the address for the branch. This address must obviously be set up prior to the branch occurring. The register pair contains the high order byte of the address in the first, or right-most register of the pair, and the low order byte of the address in the second, or left-most register of the pair, in order to maintain alignment with the general addressing scheme.
The Intel documentation divides the 8085’s instruction set into five groups. These are the Data Transfer Group, Arithmetic Group, Logical Group, Branch Group, and a Machine Control-I/O Group. These will now be discussed individually, with specific instructions mentioned for illustration in these notes. The entire set will be reviewed by the instructor as this section progresses.

Data Transfer Instructions Group

DATA TRANSFER GROUP
This group of instructions provides the 8085 with the ability to move data around inside the RAM, between the RAM and the registers of the MP, and between registers within the MP. They are important because a good deal of moving must be done to offset the fact that in an 8-bit byte, there is insufficient room to define the operands as specifically as is done, for example, in the PDP11. These instructions do not affect the condition codes. A few comments on the OP code groups follow:
MOV GROUP: These three instructions (MOV r1,r2, MOV r,M, and MOV M,r) are the general means of moving data between memory and registers. They move one byte with each execution. The second and third examples illustrate the use of the Register Indirect mode of addressing, in which the H&L registers of the MP contain an address, and the data is moved to or from that address. This saves space, in that the instruction is only one byte long. It requires, however, that the H&L registers be previously set up with the address required. The letter "M", when appearing as an operand in this description, specifies Register Indirect mode with H&L as the register to contain the address. No other register pair is used as such.
MVI GROUP: These two instructions (MVI r,data, and MVI M,data) provide a means of loading a byte immediately into a register or a memory address. Note that the Register Indirect mode again is evident. The immediate data is stored as a byte directly below the instruction byte.
LXI INSTRUCTION: This single instruction (LXI rp,data 16) provides a means of loading any register pair with a two-byte value. The second byte l of the instruction is loaded into the leftmost, or low-order, register of the pair, while the third byte is loaded into the rightmost, or high order, register of the pair.
LDA & STA: The Load Accumulator Direct (LDA) and the Store Accumulator Direct (STA) instructions provide a means of moving a byte between the accumulator and a RAM address. This may also be done with the MOV OP code, but only indirectly, that is, with the help of the H&L registers. The address of the byte to be loaded or stored follows the instruction, again with the inverse addressing.
LHLD & SHLD: The Load H&L Direct (LHLD) and Store H&L Direct (SHLD) instructions provide a means of moving two bytes between the HL register pair and a RAM address. Since the H&L register pair is heavily used in the Register Indirect mode, these instructions provide a quick means of loading the two bytes of an address into the pair in only one instruction. The two bytes following the instruction contain an address in RAM, again low-order in byte 2, and high-order in byte 3. For the LHLD, this address points to a single byte, which is obtained and loaded into the L register. The second byte from RAM is obtained from the address one higher than the RAM byte, and loaded into the H register. The SHLD simply stores as above, instead of loads.
LDAX & STAX: The Load Accumulator Indirect (LDAX) and Store Accumulator Indirect (STAX) instructions provide a means of moving data between the U accumulator and a memory location indirectly, with the RAM address contained in either the BC or DE register pair. This is not the same as the MOV, which uses only the HL register pair. This instruction permits the accumulator to access groups of data bytes, as may be necessary with long precision arithmetic. Obviously, the BC or DE pair must be previously loaded with the address desired.
XCHG INSTRUCTION: The Exchange (XCHG) instruction permits the HL register pair’s contents to be exchanged with the DE register pair’s contents. This allows an address to be built in the DE pair, then, when ready, to be transferred at once to the HL pair. This would be advantageous in complex data handling.

Arithematic Instruction Group.

ARITHMETIC GROUP
This group provides the 8085 with mathematical ability to manipulate 8-bit data, and, by judicious use of the condition codes, to manipulate larger values. The A register (Accumulator) can perform true adds, subtracts, and compares. The other registers can only increment or decrement by 1. Unless otherwise indicated, all the condition code flags are affected. A few comments follow:
ADD INSTRUCTIONS: The Add Register (ADD r) and Add Memory (ADD M) instructions add the byte specified, either in a register or in the address contained by the H&L registers, into the accumulator. They assume that the accumulator already has in it the other value to participate in the add. The sum will remain in the accumulator. If the answer resulted in a ninth bit, it is stored in the Carry flag of the PSW.
ADD WITH CARRY: The Add Register with Carry (ADC r) and Add Memory with Carry (ADC M) instructions will add the specified byte, either in a register or in the address contained by the H&L registers, AND the value of the Carry bit, into the accumulator. By including the carry bit in the operation, mathematical operations on values longer than 8 bits are possible. As above, the first value must already be loaded in the A register prior to execution of these instructions. The sum remains in the accumulator. If the answer resulted in a ninth bit, it is stored in the Carry flag.
ADD IMMEDIATES: The Add Immediate (ADI) and Add Immediate with Carry (ACI) instructions provide a means of adding a fixed value into the accumulator. These instructions assume that an initial value has already been loaded into the accumulator. The immediate data is provided by the second byte of the instruction. The ACI instruction adds the immediate value and the value of the Carry flag, while the ADI does not take the Carry flag into account. The sum remains in the accumulator. If the answer resulted in a ninth bit, it is stored in the Carry flag.
SUBTRACT INSTRUCTIONS: The Subtract Register (SUB r) and the Subtract Memory (SUB M) instructions subtract the specified byte, in a register or in the address contained by the H&L registers, from the contents of the accumulator. The accumulator must have the first value already loaded , prior to the execution of the instructions. The subtract is accomplished by the complement-and-add technique, in which the two’s complement of the specified value is computed first, and then added to the contents of the A register. The Carry flag will be set to a 1 if a borrow was required during the subtraction.
SUBTRACT WITH BORROW: The Subtract Register with Borrow (SBB r) and the Subtract Memory with Borrow (SBB M) instructions will subtract the specified byte, either in a register or in the address contained in the H&L registers, and the value of the Carry flag, from the contents of the A register. The first value must be loaded into the A register prior to the execution of the instructions. The subtract is accomplished by the complement-and-add technique. The Carry flag will be set to a 1 if a borrow was required during the subtraction.
SUBTRACT IMMEDIATES: The Subtract Immediate (SUI data) and Subtract Immediate with Borrow (SBI data) instructions provide a means of subtracting a fixed value from the contents of the accumulator. The immediate value is provided by the second byte of the instruction. The first value must be loaded into the accumulator prior to the execution of the instructions. The subtract is accomplished by the complement-and-add technique. The SBI instruction will subtract both the immediate value and the contents of the Carry flag from the A register, while the SUI does not take the Carry flag into account. The Carry flag will be set at the end of the instruction if , a borrow was required during execution.
INCREMENT INSTRUCTIONS: The Increment Register (INR r) and Increment Memory (INR M) instructions provide a quick means of adding one to the contents of a register or memory location. These instructions allow the programmer to create counting routines and reiterations. Note that the Carry flag is not affected by these instructions.
DECREMENT INSTRUCTIONS: The Decrement Register (DCR r) and Decrement Memory (DCR M) instructions provide a quick means of subtracting one from the contents of a register or a memory location. These instructions allow the programmer to create counting routines and reiterations. Note that the Carry flag is not affected by these instructions.
REGISTER PAIR INSTRUCTIONS: The Increment Register Pair (INX rp) and Decrement Register Pair (DCX rp) instructions provide a means of adding to, or subtracting from, a 16-bit value contained in a register pair. In the INX instruction, this means that the carry from the sum of the low order byte of the pair and the one will be added into the upper byte automatically. In the DCX instruction, this means that a borrow from the high-order byte, if required, will be allowed into the low-order byte, if the subtraction of one from the low-order byte demands it. Note that none of the flags are affected.
D0UBLE ADD: The Add Register Pair to H&L (DAD rp) instruction adds a 16 bit value already existing in the BC or DE register pair into the 16-bit value contained in the H&L registers. The sum remains in the H&L registers. The Carry flag will be set if a carry occurred out of the high order byte; a carry from low- to high-order bytes within the add is taken into account automatically. This instruction allows a fixed index-like value to be added to the H&L registers for Register Indirect mode.
DECIMAL ADJUST: The Decimal Adjust Accumulator (DAA) instruction converts the 8-bit value in the A register, which normally is assumed to be two 4bit hexadecimal values, into two 4-bit BCD values. This allows the programmer to accept input data as BCD, process it in the accumulator using essentially hexadecimal arithmetic, and then convert the result back into BCD. This may be done by virtue of the fact that the ten numbers of BCD (0 to 9) are coded in binary exactly as are the first ten of the sixteen numbers of binary coded hexadecimal. i.e., adding 3810 and 3816 are exactly the same. The conversion be may accomplished by the use of the Auxiliary Carry flag. If the contents of the low-order four bits of the A register is >9, or if the AC flag is set, a value of 6 is added to these bits. Then the high-order four bits of the A register are examined; again, if they contain a value >9, or if the Carry flag is on, a 6 is added to them. The Carry flag, of course, indicates that the hexadecimal value of the byte before the instruction, when translated to BCD, is too large to fit in one byte.